金宝appMATLAB支持数据类型、运算符和控制器l Flow Statements

When you generate HDL code from your MATLAB^®算法，使用HDL Coder™支持的数据类型，运算符和控制流语句。金宝app

金宝app支持的数据类型

HDL编码器不支持单元格数和金宝appinf数据类型. This table shows the supported subset of MATLAB data types.

Types	金宝app支持的数据类型	Restrictions
Integer	`uint8`,`uint16`,`uint32`,`uint64` `int8`,`INT16`,`INT32`,`int64`	In Simulink^®,MATLAB Functionblock ports must use numeric types`sfix64`或者`ufix64`for 64-bit data.
真实的	`double` `single`	HDL代码生成`double`或者`single`数据类型in your MATLAB code can be used for simulation, but is not synthesizable. You can generate synthesizable code when you use these data types in your Simulink model. For more information, see: Simulink Blocks Supported with Native Floating-Point 用本机浮点生成独立于目标的HDL代码 Signal and Data Type Support
特点	`char`	–
Logical	`logical`	–
Fixed point	Scaled (binary point only) fixed-point numbers 定制整数（零二进制点）	Fixed-point numbers with slope (not equal to 1.0) and bias (not equal to 0.0) are not supported. 定点数字的最大单词大小为128位。
Vectors	无序`{n}` 排`{1, N}` column`{N, 1}`	允许的最大矢量元素数为2^32。 Before a variable is subscripted, it must be fully defined.
Matrices	`{n，m}`	矩阵在设计算法的主体中受支金宝app持，但不支持顶级设计功能的输入。 Do not use matrices in the testbench.
Structures	`struct`	Arrays of structures are not supported. 对于FPGA交钥匙和IP核心生成工作流程，设计算法的主体支持结构，但不受支持作为顶级设计功能的输入。金宝app
枚举	`enumeration`	Enumeration values must be monotonically increasing. If your target language is Verilog^®，所有枚举成员名称必须在设计中唯一。枚举at the top-level DUT ports are not supported with the following workflows or verification methods: IP Core Generation workflow FPGA Turnkey workflow FPGA在环 HDL共同模拟

Global variables are not supported for HDL code generation.

Supported Operators

Note

针对大型矢量和算术操作的矩阵输入生成的HDL代码可能导致效率低下的代码。这些运算符的代码不会自动管道。

Arithmetic Operators

手术	Operator Syntax	Equivalent Function	Restrictions
Binary addition	`a+b`	`plus(A,B)`	Neither`A`nor`B`can be data type`logical`.
Matrix multiplication	`A*B`	`mtimes(A,B)`	HDL code generated for matrix arithmetic operations is not pipelined, and can result in inefficient code.
Arraywise multiplication	`A.*B`	`时间（A，B）`	Neither`A`nor`B`can be data type`logical`.
Matrix power	`a^b`	`mpower(A,B)`	`A`和`B`must be scalar, and`B`must be an integer. HDL code generated for matrix arithmetic operations is not pipelined, and can result in inefficient code.
阵列的功率	`A.^B`	`power(A,B)`	`A`和`B`must be scalar, and`B`must be an integer.
Complex transpose	`A'`	`ctranspose(A)`	–
Matrix transpose	`一个。'`	`transpose(A)`
矩阵concat	`[A B]`	没有任何	–
Matrix index	`A(r c)`	没有任何	在使用变量之前，必须完全定义它。

逻辑操作员

手术	Operator Syntax	M Function Equivalent	Notes
Logical And	`A&B`	`和(A,B)`	–
Logical Or	`A\|B`	`或者(A,B)`	–
Logical Xor	`A xor B`	`xor(A,B)`	–
Logical And (short circuiting)	`A && b`	N/A	Use short circuiting logical operators within conditionals.
逻辑或（短路）	`A\|\|B`	N/A	Use short circuiting logical operators within conditionals.
Element complement	`〜a`	`not(A)`	–

关系运营商

Relation	Operator Syntax	Equivalent Function
Less than	`a`	`lt(A,B)`
Less than or equal to	`A<=B`	`le(A,B)`
Greater than or equal to	`A>=B`	`ge(A,B)`
Greater than	`a> b`	`gt(A,B)`
Equal	`A==B`	`等式（A，B）`
不相等	`A~=B`	`NE（A，B）`

控制流语句

HDL Coder supports the following control flow statements and constructs with restrictions.

Control Flow Statement Restrictions

Control Flow Statement	Restrictions
`for`	Do not use`for`循环无静态界限。 Do not use the`&`和`\|`运营商在一个条件下`for`陈述。而是使用`&&`和`\|\|`操作员。 HDL Coder does not support nonscalar expressions in the conditions of`for`语句。而是使用`全部`或者`任何`functions to collapse logical vectors into scalars.
`if`	Do not use the`&`和`\|`运营商在一个条件下n`if`陈述。而是使用`&&`和`\|\|`操作员。 HDL Coder does not support nonscalar expressions in the conditions of`if`语句。而是使用`全部`或者`任何`functions to collapse logical vectors into scalars.
`转变`	在A中的条件表达`转变`或者`case`statement must use only: `uint8`,`uint16`,`uint32`,`int8`,`INT16`, or`INT32`数据类型 Scalar data 如果多个`case`statements make assignments to the same variable, the numeric type and`fimath`该变量的规范必须相同`case`陈述。

for

Do not usefor循环无静态界限。

Do not use the&和|运营商在一个条件下for陈述。而是使用&&和||操作员。

HDL Coder does not support nonscalar expressions in the conditions offor语句。而是使用全部或者任何functions to collapse logical vectors into scalars.

if

Do not use the&和|运营商在一个条件下nif陈述。而是使用&&和||操作员。

HDL Coder does not support nonscalar expressions in the conditions ofif语句。而是使用全部或者任何functions to collapse logical vectors into scalars.

转变

在A中的条件表达转变或者casestatement must use only:

uint8,uint16,uint32,int8,INT16, orINT32数据类型
Scalar data

如果多个casestatements make assignments to the same variable, the numeric type andfimath该变量的规范必须相同case陈述。

The following control flow statements are not supported:

尽管
break
continue
返回
parfor

Avoid using the following vector functions, as they may generate loops containingbreakstatements:

isequal
BitRevorder

HDL Coder Documentation

金宝app

Deploying 5G NR Wireless Communications on FPGAs: A Complete MATLAB and Simulink Workflow

下载白皮书