Import HDL Code for HDL Cosimulation Block

Cosimulation Type—金宝appBlock

Open your model, and on theAppstab, clickHDL Verifier. Then, in theModesection selectHDL Cosimulation, and clickImport HDL Filesto open theCosimulation Wizard.

SelectModelSim,Xcelium, orVivado Simulatorfor theHDL Simulator.
SelectUse HDL simulator executables on the system pathif that is where the files are located. The Cosimulation Wizard assumes by default that they are on the system path.
If the HDL simulator executables arenoton the system path, selectUse the following HDL simulator executables at the following locationand specify the folder location in the text box below.
If you clickNextand the Cosimulation Wizard does not find the executables, the following occurs:
- You are returned to this dialog and the Cosimulation Wizard displays an error in the status pane.
- The Cosimulation Wizard switches the option toUse the following HDL simulator executables at the following location.
- The Cosimulation Wizard makes the HDL simulation path field editable.
You must enter a valid path to the HDL simulator executables before you are allowed to continue.
ClickNext.

HDL Files—金宝appBlock

In theHDL Filespane, specify the files to be used in creating the function or block.

Cosimulation向导试图确定file type of each file and display the type in theFile Listnext to the file name. If the Cosimulation Wizard cannot determine the type or displays the wrong type, you can change the type directly in theFile Typecolumn.
If possible, the Cosimulation Wizard will determine the compilation order automatically using HDL simulator provided functionality. This means you can add the files in any order.
If you are using ModelSim^®, you will see compilation scripts listed as .do files (ModelSim macro file). If you are using Xcelium™, you will see compilation scripts listed as system scripts.

ClickAddto select one or more file names.
Remove files by first highlighting the file name in theFile List, then clickingRemove Selected File.
ClickNext.

HDL Compilation—金宝appBlock

In theHDL Compilationpane, you can review the generated HDL compilation commands. You may override and/or customize those commands, if you wish. If you included compilation scripts instead of HDL files, this pane will show you the command to run those scripts.

Enter any changes to the commands in theCompilation Commandsbox.
Note

Do not include system shell commands; for example:
```
set file = a.vhd vcom $file
```
When control returns to the Cosimulation Wizard from executing the command, the variable no longer holds the value that was set. If you do try to include this type of command, you will see an error in theStatus面板。
ClickRestore default commandsto go back to the generated HDL compilation commands. You are asked to confirm that you want to discard any changes.
ClickNextto proceed.

Simulation Options—金宝appBlock

Modelsim or Xcelium Users:

The cosimulation wizard is open on Simulation Options pane, configured for Modelsim.

In theSimulation Optionspane, provide the name of the HDL module to be used in cosimulation.

Enter the name of the module atName of HDL module to cosimulate with.
Specify additional simulation options atSimulation options. For example, in the previous image, the options shown are:
- HDL simulator resolution
- Turn off optimizations that remove signals from the simulation view
ClickRestore Defaultsto change the options back to the default.
ForConnection method, selectShared Memoryif your firewall policy does not allow TCP/IP socket communication.
ClickNextto proceed to the next step. At this time in the process, the application performs the following actions in a command window:
- Starts the HDL simulator.
- Loads the HDL module in the HDL simulator.
- Starts the HDL server, and waits to receive notice that the server has started.
- Connects with the HDL server to get the port information.
- Disconnects and shuts down the HDL server.
ClickingNextalso generates a parameter configuration file. For more information, seeUse HDL Parameters in Cosimulation.
Vivado Simulator Users:

When creating a system object for Vivado^®cosimulation, the wizard displays the name of the HDL top module.
To generate a waveform file, setDebug internal signalstowave.
In theHDL time precisionparameter you can also change the simulation time precision.
ClickNextto create a shared library (dll file).
For Vivado cosimulation, this step creates a shared library.

Input/Output Ports—金宝appBlock

In theSimulink Ports窗格中,指定type of each input and output port.
- Cosimulation向导试图确定port types for you, but you may override any setting. For supported data types, seeSupported Data Types.
- For input ports, selectInput,Clock,Reset, orUnused.
- For output ports, selectOutputorUnused.
- 金宝app^®forces clock and reset signals in the HDL simulator through Tcl commands. You can specify clock and reset signal timing in a later step (seeClock/Reset Details—Simulink Block).
- To drive your HDL clock and reset signals with Simulink signals, mark them asInput.
ClickNextto proceed toOutput Port Details—Simulink Block.

Output Port Details—金宝appBlock

In theOutput Port Detailspane, set the sample time and data type for all output ports.
- Sample time default is1, the data type default isInheritandSigned. These defaults are consistent with the way theHDL Cosimulationblock mask (Portstab) sets default settings for output ports.
- If you selectSet all sample times and data types to 'Inherit', the ports inherit the times via back propagation (sample times are set to -1). However, back propagation may fail in some circumstances; seeBackpropagation in Sample Times(Simulink).
ClickNext.

Clock/Reset Details—金宝appBlock

In theClock/Reset Detailspane, set the clock and reset parameters.
- The time period specified here refers to time in the HDL simulator.
- The clock default settings are a rising active edge and a period of 10 ns.
- The reset default settings are an initial value of 0 and a duration of 15 ns.
The next screen provides a visual display of the simulation start time where you can review how the clocks and resets line up.
ClickNext.

Start Time Alignment—金宝appBlock

In theStart Time Alignmentpane, review the current settings for clocks and resets. The purpose for this dialog is twofold:
- To make sure the rising or falling edge is set as expected (from the previous step)
  - Examine the start time. If it coincides with the active edge of the clock, you need to adjust the HDL simulator start time.
  - Examine the reset signal. If it is synchronous with the clock active edge, you may have a possible race condition.
    To avoid a race condition, make sure the start time does not coincide with the active edge of any clocks. You can do this by moving the start time or by changing clock active edges in the previous step.
- To make sure the start time is where you want it.
从th HDL模拟器计算开始时间e clock and reset values on the previous pane. If you want, you can change the HDL simulator start time by entering a new value where you seeHDL time to start cosimulation (ns). ClickUpdate plotto see your change applied.
ClickNext.

Generate Block

Specify if you want HDL Verifier™ to determine the timescale when you start the simulation by selectingAutomatically determine timescale at start of simulation. If you prefer to determine the timescale yourself, leave this box unchecked and enter the timescale value in the text boxes below. The default is to automatically determine timescale.
For more about timescales, seeSimulation Timescales.
ClickBackto review or change your settings.
ClickFinishto generate the HDL cosimulation block.

Complete金宝appModel

TheCosimulation Wizardtool inserts the following items to your model:

ModelSimorXceliumusers:

AnHDL Cosimulationblock
A utility function to compile the HDL design
A utility function to launch the HDL simulator

Simulink canvas with a Modelsim Cosimulation block, a block labeled

Vivadousers:

AnHDL Cosimulationblock
A utility block to generate a DLL file

Simulink canvas with a Vivado Cosimulation block, and another block labeled

Place the block so that the inputs and outputs to theHDL Cosimulationblock line up.
Connect the blocks in the destination model to theHDL Cosimulationblock.

Note

If you opened theCosimulation Wizardfrom the command line and not from the Simulink toolstrip, theHDL Cosimulationand the utility functions open in a new model. You first have to copy them to your model.

When you have completed the model, seePerforming Cosimulationfor the next steps in HDL cosimulation.