Unit Delay

Delay signal one sample period

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库:
Simulink / Discrete
HDL Coder / Discrete

Description

TheUnit Delayblock holds and delays its input by the sample period you specify. When placed in an iterator subsystem, it holds and delays its input by one iteration. This block is equivalent to the z^-1discrete-time operator. The block accepts one input and generates one output. Each signal can be scalar or vector. If the input is a vector, the block holds and delays all elements of the vector by the same sample period.

You specify the block output for the first sampling period with theInitial conditionsparameter. Careful selection of this parameter can minimize unwanted output behavior. You specify the time between samples with theSample timeparameter. A setting of-1means the block inherits theSample time.

Note

TheUnit Delayblock errors out if you use it to create a transition between blocks operating at different sample rates. Use theRate Transitionblock instead.

Comparison with Similar Blocks

The内存,Unit Delay, andZero-Order Holdblocks provide similar functionality but have different capabilities. Also, the purpose of each block is different.

This table shows recommended usage for each block.

Block	Purpose of the Block	Reference Examples
Unit Delay	Implement a delay using a discrete sample time that you specify. The block accepts and outputs signals with a discrete sample time.	Engine Timing Model with Closed Loop Control(Compression subsystem)
内存	Implement a delay by one major integration time step. Ideally, the block accepts continuous (or fixed in minor time step) signals and outputs a signal that is fixed in minor time step.	Building a Clutch Lock-Up Model(Friction Mode Logic/Lockup FSM subsystem) Capture the Velocity of a Bouncing Ball with the Memory Block
Zero-Order Hold	Convert an input signal with a continuous sample time to an output signal with a discrete sample time.	Developing the Apollo Lunar Module Digital Autopilot Radar Tracking Using MATLAB Function Block

Each block has the following capabilities.

Capability	内存	Unit Delay	Zero-Order Hold
Specification of initial condition	Yes	Yes	No, because the block output at time t = 0 must match the input value.
Specification of sample time	No, because the block can only inherit sample time from the driving block or the solver used for the entire model.	Yes	Yes
Support for frame-based signals	No	Yes	Yes
Support for state logging	No	Yes	No

String Support

TheUnit Delayblock can accept and output string data type only if the block is configured for a delay length of0or1or for direct feedthrough.

Ports

Input

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`Port_1`— Input signal
scalar | vector

Input signal that the block delays by one sample period.

Output

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`Port_1`— Output signal
scalar | vector

Output signal that is the input delayed by one sample period.

Parameters

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Main

`Initial condition`— First sample period output
`0`(default) | scalar | vector

Specify the output of the simulation for the first sampling period, during which the output of theUnit Delayblock is otherwise undefined.

Programmatic Use

Block Parameter:InitialCondition

Type: character vector

Value: scalar | vector

Default:'0'

`Input processing`— Specify sample- or frame-based processing
`Elements as channels (sample based)`(default) |`Columns as channels (frame based)`

Specify whether the block performs sample- or frame-based processing:

Columns as channels (frame based)— Treat each column of the input as a separate channel (frame-based processing).

Note

Frame-based processing requires a DSP System Toolbox™ license.

For more information, seeSample- and Frame-Based Concepts(DSP System Toolbox).
Elements as channels (sample based)— Treat each element of the input as a separate channel (sample-based processing).

UseInput processingto specify whether the block performs sample- or frame-based processing. For more information about these two processing modes, seeSample- and Frame-Based Concepts(DSP System Toolbox).

Programmatic Use

Block Parameter:InputProcessing

Type: character vector

Values:基于列的通道(帧)的|'Elements as channels (sample based)'

Default:'Elements as channels (sample based)'

`Sample time (-1 for inherited)`— Discrete interval between sample time hits
`-1`(default) |`scalar`

Enter the discrete interval between sample time hits or specify-1to inherit the sample time.

Programmatic Use

Block Parameter:SampleTime

Type: character vector

Value: real scalar

Default:'-1'

State Attributes

`State name`— Unique name for block state
`''`(default) | alphanumeric string

Use this parameter to assign a unique name to the block state. The default is' '. When this field is blank, no name is assigned. When using this parameter, remember these considerations:

A valid identifier starts with an alphabetic or underscore character, followed by alphanumeric or underscore characters.
The state name applies only to the selected block.

This parameter enablesState name must resolve to Simulink signal objectwhen you clickApply.

For more information, seeC Code Generation Configuration for Model Interface Elements(Simulink Coder).

Programmatic Use

Block Parameter:StateName

Type:character vector

Values:unique name

Default:''

`State name must resolve to Simulink signal object`— Require state names resolve to signal object
`Off`(default) | Boolean

Specify if requiring that state name resolve to Simulink signal objects or not. If selected, the software generates an error at run time if you specify a state name that does not match the name of a Simulink signal object.

Dependency

Enabled when you give the parameterState namea value and set the model configuration parameterSignal resolutionto a value other thanNone.

Selecting this check box disablesCode generation storage class.

Programmatic Use

Block Parameter:StateMustResolveToSignalObject

Type: character vector

Values:'off'|'on'

Default:'off'

Model Examples

Engine Timing Model with Closed Loop Control

Enhance a version of the open-loop engine model described in Modeling Engine Timing Using Triggered Subsystems. This model,sldemo_enginewc, contains a closed-loop and shows the flexibility and extensibility of Simulink® models. In this enhanced model, the objective of the controller is to regulate engine speed with a fast throttle actuator, such that changes in load torque have minimal effect. This is easily accomplished in Simulink by adding a discrete-time PI controller to the engine model.

Open Model

Block Characteristics

Data Types	`Boolean`\|`bus`\|`double`\|`enumerated`\|`fixed point`\|`一半`\|`我nteger`\|`single`\|`string`
Direct Feedthrough	`yes`
Multidimensional Signals	`yes`
Variable-Size Signals	`yes`
Zero-Crossing Detection	`no`

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Generated code relies on memcpy or memset functions (strong.h) under certain conditions.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is`0`. For more details, seeInputPipeline(HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is`0`. For more details, seeOutputPipeline(HDL Coder).
ResetType	Suppress reset logic generation. The default is`default`, which generates reset logic. See alsoResetType(HDL Coder).

Complex Data Support

This block supports code generation for complex signals.

Unit Delay