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Stream from FPGA to Processor Template

Use theStream from FPGA to Processortemplate to create an SoC Blockset™ model for designing a datapath from hardware (FPGA) to software (Processor). To create a project using the "Stream to Processor" template, follow the steps toCreate SoC Model Using SoC Blockset Template.

Required Products

Forsample-basedprocessing, no additional products are required.

Forframe-basedprocessing, DSP System Toolbox™ is required.

Template Structure

This template models a counter as the test data source and minimal logic for the FPGA and processor algorithms. Use this template as a guide and replace the FPGA algorithm and Processor algorithm with your own functionality. The FPGA algorithm is a simple multiplication performed on input data from the test source and from aconfigRegparameter. The processor writes theconfigReg. This parameter is modeled using theRegister Channelblock. Data from the FPGA algorithm is passed to the processor through aMemory Channelblock. The memoryChannel Typeparameter is set toAXI4-Stream to Software via DMA, which models the DMA data transfer through shared external memory.

The processor reads the computed data from the memory and performs additional computing, which is implemented in the template as a pass-through wire. You can view the simulation results by double-clicking theVector Scopeblock in the testbench sink.

Modify Project

Modify the FPGA Model

In the MATLAB®toolstrip, on theProject Shortcutstab, clickOpen FPGA sample modelto open the FPGA model. In the model, two areas are highlighted green, which represents user code: one in the FPGA Algorithm Wrapper block and one in the Test Source Wrapper block.

  • FPGA Algorithm Wrapper – Double-click to open the model. The algorithm wrapper contains a green-highlighted subsystem namedFPGA Algorithm. This block has two inputs and one output and is implemented as a multiplier. Replace this block with your own FPGA algorithm. Add inputs and outputs as required.

  • Test Source Wrapper – This block includes a test source and is intended to generate stimulus as an input to the FPGA algorithm. This block is implemented as a counter in this template. Modify the test source to your needs, or replace it with an alternative source block.

Tip

When your FPGA model includes more than one IP, you must define each IP as a subsystem and connect the subsystems using aStream ConnectororVideo Stream Connectorblock. For additional information, seeConsiderations for Multiple IPs in FPGA Model.

To enable consistent simulation behavior, clickOpen FPGA frame modelin theProject Shortcutstab and repeat this step. To simulate frame-based processing, you must have a DSP System Toolbox license.

Modify the Processor Model

In the MATLAB toolstrip, on theProject Shortcutstab, clickOpen Processor model. The processor wrapper contains a blue highlighted subsystem representing the user code for the processor algorithm. Open the Processor Algorithm wrapper and replace theProcessor Algorithm块和你需要的算法。

Modify the Register Channel

The top model of a template also includes a register channel to communicate between the processor and the FPGA model. Use the register channel to configure the FPGA model, or to read and check status registers. TheRegister Channelblock in the template includes one register. To add additional registers you must modify the register channel block parameters, the FPGA algorithm, and the processor algorithm:

  1. Add registers to the register channel – Double-click theRegister Channelblock to open the block mask and add additional registers as needed. Adding registers creates additional ports on theRegister Channelblock. For additional information, seeRegister Channel.

  2. Add ports to the processor model – Navigate to theProcessor Algorithm Wrappermodel. To navigate to the processor model, clickOpen Processor modelon theProject Shortcutstab. Double-clickProcessor Algorithm Wrapperto modify it.

    为写瑞吉斯ters, add an output port to the module and add logic to drive a value to the added output port. For read registers, add an input port and logic to process the information returned from a read register. From the top model, wire the port to theRegister Channelblock.

  3. Add ports to the FPGA model – Navigate to theFPGA Algorithm Wrappermodel. To navigate to the FPGA/Frame based processing model, clickOpen FPGA sample modelon theProject Shortcutstab. Double-clickFPGA Algorithm Wrapperto modify it.

    为写瑞吉斯ters, add an input port to the module and logic to process the information returned from a read register. For read registers, add an output port and logic to drive a value to the added output port.

    For equivalent behavior when using a Simulink®山姆纸浆包变体,重复这个步骤ple-based processing model in the FPGA wrapper.

  4. From the top model, wire the new port to theRegister Channelblock.

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