Add enable port to subsystem or model - Simulink - MathWorks Switzerland - 金宝app,下载188bet金宝搏,金宝搏官方网站

Examples

启用子系统s

当一个正弦波输入enabled subsystem. After running the simulation, the scope shows three plots.

Open Model

Advanced Enabled Subsystems

当一个正弦波输入enabled subsystem. The four subsystems in the model contain integrators, either discrete or continuous as described by the subsystem name. After running the simulation, the two scopes show the results for the discrete enabled subsystems (top scope) and continuous enabled subsystems (bottom scope).

Open Model

Illustration of Law of Large Numbers

Use MATLAB System blocks to illustrate the law of large numbers.

Open Model

Counters Using Conditionally Executed Subsystems

The contrast between enabled subsystems and triggered subsystems for the same control signal, through the use of counter circuits. After running the simulation, the scope shows three plots.

Open Model

Merging Signals

Use conditionally executed subsystems and theMergeblock to combine two inputs into a single output.

Open Model

Building a Clutch Lock-Up Model

Use Simulink® to model and simulate a rotating clutch system. Although modeling a clutch system is difficult because of topological changes in the system dynamics during lockup, this example shows how Simulink's enabled subsystems easily handle such problems. We illustrate how to employ important Simulink modeling concepts in the creation of the clutch simulation. Designers can apply these concepts to many models with strong discontinuities and constraints that may change dynamically.

Open Model

Ports

Output

expand all

Enable signal—External enable signal for a subsystem or model
scalar

Enable signal attached externally to the outside of an启用子系统block and passed to the inside of the subsystem. An enable signal port is added to anEnableblock when you select theShow output portparameter.

Parameters

expand all

States when enabling—Select block states when subsystem or model is disabled
`held`(default) |`reset`

When aSubsystemblock orModelblock is disabled, select what happens to block states for the blocks within the subsystem or model.

held: Hold block states at their previous values.
reset: Reset block states to their initial conditions (zero if not defined).

Programmatic Use

Block parameter:StatesWhenEnabling

Type:character vector

Values:'held'|'reset'

Default:'held'

Propagate sizes of variable-size signals—Select when to propagate a variable-size signal
`Only when enabling`(default) |`During execution`

Select when to propagate a variable-size signal.

Only when enabling: Propagate a variable-size signal when reenabling aSubsystemblock orModelblock containing anEnableport block. When you select this option, sample time must be periodic.
During execution: Propagate variable-size signals at each time step.

Programmatic Use

Block parameter:PropagateVarSize

Type:character vector

Values:'Only when enabling'|'During execution'

Default:'Only when enabling'

Show output port—Control display of output port for enable signal
off (default) | on

The output port passes the enable signal attached externally to the outside of an启用子系统block or enabledModelblock to the inside.

off: Remove the output port on theEnableport block.
on: Display an output port on theEnableport block. Selecting this option allows the subsystem or model to process the enable signal.

Programmatic Use

Block parameter:ShowOutputPort

Type:character vector

Values:'off'|'on'

Default:'off'

Enable zero-crossing detection—Control zero-crossing detection
on (default) | off

Control zero-crossing detection for a model.

on: Detect zero crossings.
off: Do not detect zero crossings.

Programmatic Use

Block parameter:ZeroCross

Type:character vector

Values:'on'|'off'

Default:'on'

Port dimensions—Specify dimensions for the enable signal
`1`(default) |`[n]`|`[m n]`

Specify dimensions for the enable signal attached externally to aModelblock and passed to the inside of the block.

1: Scalar signal.
[n]: Vector signal of widthn.
[m n]: Matrix signal havingmrows andncolumns.

Programmatic Use

Block parameter:PortDimensions

Type:character vector

Values:'1'|'[n]'|'[m n]'

Default:'1'

Sample time—Specify time interval
`-1`(default) |`Ts`|`[Ts, To]`

Specify time interval between block method execution. SeeSpecify Sample Time.

-1: Sample time inherited from the model.
Ts: Scalar where Ts is the time interval.
[Ts, To]: Vector where Ts is the time interval and To is the initial time offset.

Programmatic Use

Block parameter:SampleTime

Type:character vector

Values:'-1'|'Ts'|'[Ts, To]'

Default:'-1'

Minimum—Specify minimum output value for the enable signal
`[]`(default) | real scalar

Specify minimum value for the enable signal attached externally to aModelblock and passed to the inside of the block.

金宝app^®uses this value to perform:

Simulation range checking. SeeSpecify Signal Ranges.
Automatic scaling of fixed-point data types.
Optimization of generated code. This optimization can remove algorithmic code and affect the results of some simulation modes such as SIL or external mode. SeeOptimize using the specified minimum and maximum values(Embedded Coder).

[]: Unspecified minimum value.
real scalar: Real double scalar value.

Programmatic Use

Block parameter:OutMin

Type:character vector

Values:'[]'|''

Default:'[]'

最大—Specify maximum output value for the enable signal
`[]`(default) | real scalar

Specify maximum value for the enable signal attached externally to aModelblock and passed to the inside of the block.

Simulink uses this value to perform:

Simulation range checking. SeeSpecify Signal Ranges.
Automatic scaling of fixed-point data types.
Optimization of generated code. This optimization can remove algorithmic code and affect the results of some simulation modes such as SIL or external mode. SeeOptimize using the specified minimum and maximum values(Embedded Coder).

[]: Unspecified maximum value.
real scalar: Real double scalar value.

Programmatic Use

Block parameter:OutMax

Type:character vector

Values:'[]'|''

Default:'[]'

Data type—Specify output data type for the enable signal
`double`(default) |`single`|`int8`|`uint8`|`int16`|`uint16`|`int32`|`uint32`|`int64`|`uint64`|`boolean`|`fixdt(1,16)`|`fixdt(1,16,0)`|`fixdt(1,16,2^,0)`|

Specify data type for the enable signal attached externally to aModelblock and passed to the inside of the block.

double: Double-precision floating point.
single: Single-precision floating point.
int8: Signed 8-bit integer.
uint8: Unsigned 8-bit integer.
int16: Signed 16-bit integer.
uint16: Unsigned 16-bit integer.
int32: Signed 32-bit integer.
uint32: Unsigned 32-bit integer.
int64: Signed 64-bit integer.
uint64: Unsigned 64-bit integer.
boolean: Boolean with a value oftrueorfalse.
fixdt(1,16): Signed 16-bit fixed point number with binary point undefined.
fixdt(1,16,0): Signed 16-bit fixed point number with binary point set to zero.
fixdt(1,16,2^,0): Signed 16-bit fixed point number with slope set to2^0and bias set to0.
: Data type object, for exampleSimulink.NumericType. You cannot enter the name of aSimulink.Busobject as a data type expression.

Programmatic Use

Block parameter:OutDataTypeStr

Type:character vector

Default:'double'

Mode—Select data type category
`Build in`(default) |`Fixed point`|`Expression`

Select data type category and display drop-down lists to help you define the data type.

Build in: Display drop-down lists for data type and Data type override.
Fixed point: Display drop-down lists for Signedness, Scaling, and Data type override.
Expression: Display text box for entering an expression.

Dependency

To enable this parameter, select the Show data type assistant button.

Programmatic Use

No equivalent command-line parameter.

Interpolate data—Specify value of missing workspace data
on (default) | off

Specify value of missing workspace data when loading data from the workspace.

on: Linearly Interpolate output at time steps for which no corresponding workspace data exists.
off: Do not interpolate output at time steps. The current output equals the output at the most recent time step for which data exists.

Programmatic Use

Block parameter:Interpolate

Type:character vector

Values:'on'|'off'

Default:'on'

Block Characteristics

Data Types	`Boolean`\|`double`\|`fixed point`\|`integer`\|`single`
Direct Feedthrough	`no`
Multidimensional Signals	`yes`
Variable-Size Signals	`no`
Zero-Crossing Detection	`yes`

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is`0`. For more details, seeConstrainedOutputPipeline(HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is`0`. For more details, seeInputPipeline(HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is`0`. For more details, seeOutputPipeline(HDL Coder).

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

‘茵特罗德女士’uced before R2006a

Enable

Description

Examples

启用子系统s

Advanced Enabled Subsystems

Illustration of Law of Large Numbers

Counters Using Conditionally Executed Subsystems

Merging Signals

Building a Clutch Lock-Up Model

Ports

Output

Enable signal—External enable signal for a subsystem or modelscalar

Parameters

States when enabling—Select block states when subsystem or model is disabledheld(default) |reset

Programmatic Use

Propagate sizes of variable-size signals—Select when to propagate a variable-size signalOnly when enabling(default) |During execution

Programmatic Use

Show output port—Control display of output port for enable signaloff (default) | on

Programmatic Use

Enable zero-crossing detection—Control zero-crossing detectionon (default) | off

Programmatic Use

Port dimensions—Specify dimensions for the enable signal1(default) |[n]|[m n]

Programmatic Use

Sample time—Specify time interval-1(default) |Ts|[Ts, To]

Programmatic Use

Minimum—Specify minimum output value for the enable signal[](default) | real scalar

Programmatic Use

最大—Specify maximum output value for the enable signal[](default) | real scalar

Programmatic Use

Data type—Specify output data type for the enable signaldouble(default) |single|int8|uint8|int16|uint16|int32|uint32|int64|uint64|boolean|fixdt(1,16)|fixdt(1,16,0)|fixdt(1,16,2^,0)|

Programmatic Use

Mode—Select data type categoryBuild in(default) |Fixed point|Expression

Dependency

Programmatic Use

Interpolate data—Specify value of missing workspace dataon (default) | off

Programmatic Use

Block Characteristics

Extended Capabilities

C/C++ Code GenerationGenerate C and C++ code using Simulink® Coder™.

HDL Code GenerationGenerate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code GenerationGenerate Structured Text code using Simulink® PLC Coder™.

Fixed-Point ConversionDesign and simulate fixed-point systems using Fixed-Point Designer™.

Version History

See Also

Topics

Enable signal—External enable signal for a subsystem or model
scalar

States when enabling—Select block states when subsystem or model is disabled
`held`(default) |`reset`

Propagate sizes of variable-size signals—Select when to propagate a variable-size signal
`Only when enabling`(default) |`During execution`

Show output port—Control display of output port for enable signal
off (default) | on

Enable zero-crossing detection—Control zero-crossing detection
on (default) | off

Port dimensions—Specify dimensions for the enable signal
`1`(default) |`[n]`|`[m n]`

Sample time—Specify time interval
`-1`(default) |`Ts`|`[Ts, To]`

Minimum—Specify minimum output value for the enable signal
`[]`(default) | real scalar

最大—Specify maximum output value for the enable signal
`[]`(default) | real scalar

Data type—Specify output data type for the enable signal
`double`(default) |`single`|`int8`|`uint8`|`int16`|`uint16`|`int32`|`uint32`|`int64`|`uint64`|`boolean`|`fixdt(1,16)`|`fixdt(1,16,0)`|`fixdt(1,16,2^,0)`|

Mode—Select data type category
`Build in`(default) |`Fixed point`|`Expression`

Interpolate data—Specify value of missing workspace data
on (default) | off

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.