Requirements and Prerequisites

Set Up FPGA Development Board

1. Confirm that the power switch is off.

2. Connect the JTAG download cable between the FPGA development board and the host computer.

3. (Optional) Connect the line-in port of the FPGA board with an audio source, such as your cellphone, via a 3.5 mm audio cable. If you skip this step, the captured data is random noises.

Prepare Example Resources

Set up the Intel Quartus. This example assumes that the Intel Quartus executable is located in the fileC:\altera\18.0\quartus\bin\quartus.exe。如果你的可执行文件的位置是不同的,use your path instead.

hdlsetuptoolpath('ToolName','Altera Quartus II', ... 'ToolPath','C:\altera\18.0\quartus\bin\quartus.exe');

Generate FPGA Data Capture Components

Launch theFPGA Data Capture Component Generatortool by executing this command in MATLAB.

generateFPGADataCaptureIP

This example monitors two signals from the existing HDL design for the audio system: 12 bitadc_outand 8 bitcounter。Theadc_outsignal is the digital samples of the audio line-in signal. The next signalcounteris an 8 bit free-running counter. To configure the data capture components to operate on these two signals, follow these steps.

1. Add one row to thePortstable by clicking theAddbutton once.

2. Name the first signal toadc_outand the second signal tocounter。

3. Change the bit widths of the two signals to 12 and 8, respectively.

4. SelectFPGA vendorasAltera。

5. SelectGenerated IP languageasVerilog。

6. SelectSample depthas1024。This value is the number of samples of each signal that the data capture tool returns to MATLAB each time a trigger is detected.

7. SelectMax trigger stagesas2。This value is the maximum number of trigger stages that you can add during data capture to provide multiple trigger conditions.

This figure shows these tool settings.

To generate the FPGA data capture component, clickGenerate。A report shows the results of the generation.

Integrate FPGA Data Capture HDL IP

You must include the generated HDL IP core into the example FPGA design. You can copy the module instance code from the generated report. In this example, connect the generated HDL IP with the ADC output and the 8 bit free-running counter.

Open theadc_top.vfile provided with this example. Uncomment this code.

datacapture u0 ( .clk(adc_clk), .clk_enable(adc_valid), .ready_to_capture(), .adc_out(adc_out), .counter(counter[7:0]));

Saveadc_top.v, compile the modified FPGA design, and create an FPGA programming file by using the following Tcl script.

system('quartus_sh -t adc_deca_max10.tcl &')

The Tcl scripts that are included in this example perform these steps.

1. Create a new Quartus project.

2. Add example HDL files and the generated FPGA data capture HDL files to the project.

3. Compile the design.

4. Program the FPGA.

Wait until the Quartus process successfully finishes before going to the next step. This process takes approximately 5 to 10 minutes.

Capture Data

Navigate to the directory where the FPGA data capture component is generated.

cd hdlsrc

Launch theFPGA Data Capturetool. This tool is customized for the data capture signals.

launchDataCaptureApp

To start data capture, clickCapture Data。Data capture object requests one buffer of captured data from the FPGA. The default setting is to capture immediately, without waiting for a trigger condition.

The captured data is saved into a structure,dataCaptureOut, in the MATLAB workspace. If you have the DSP System Toolbox™ software, the captured data is also displayed as signal waveforms in theLogic Analyzertool.

Narrow Scope of Data Capture Using Triggers

从台塑捕捉数据A around a particular event, you can configure trigger conditions in theFPGA Data Capturetool. For example, to capture the audio data only after a counter reaches a certain value.

SelectNumber of trigger stagesas1。In theTrigger Stage 1section, selectSignalascounter。Enable this trigger signal by clicking the+button. Select the corresponding trigger condition value (Value) as10。The trigger mode automatically changes toOn trigger。This change tells the FPGA to wait for the trigger condition before capturing and returning data. This figure shows these tool settings.

ClickCapture Dataagain. This time, the data capture IP returns 1024 samples, captured when it detects that the counter equals 10.

从台塑捕捉数据A for specific bits in the trigger value, irrespective of other bits, you can configure the trigger condition with a bit-masked value.

For example, to capture an audio data only when the seventh bit of the counter is 1, set the trigger condition value (Value) to0bX1XXXXXXas this figure shows.

ClickCapture Dataagain.

The data capture IP triggers to capture the audio data for counter values in the range [64, 127] and [192, 255].

Capture Multiple Occurrences of Event

To capture a recurring event from the FPGA, configureNumber of capture windowsin theFPGA Data Capturetool.

For example, to capture the audio data at eight different time slots, selectNumber of capture windowsas8。This figure shows the updated tool settings.

ClickCapture Data。The data capture IP returns eight windows of 128 samples each, which amounts to a total sample depth of 1024.

Window depth = Sample depth/Number of capture windows;

TheLogic Analyzertool shows this result as eight occurrences of the trigger, with the audio data logged for 128 samples each.

The signalsCapture WindowandTrigger Positionindicate the corresponding window number and trigger position, respectively.

Capture Data in Multiple Trigger Stages

This scenario explains how to capture data by providing a sequence of trigger conditions in multiple trigger stages. For capturing data in multiple trigger conditions, you must selectNumber of trigger stagesas a value greater than 1 in theFPGA Data Capturetool.

For example, to capture an audio data when the counter value reaches from 0 to 5 in 5 clock cycles, follow these steps.

1. SelectNumber of trigger stagesas2。

2. In theTrigger Stage 1section, selectSignalascounter。Enable this trigger signal by clicking the+button . Select the corresponding trigger condition value (Value) as0。

3. InTrigger Stage 2section, select Signal ascounter。Enable this trigger signal by clicking the+button. Select the corresponding trigger condition value (Value) as5。SelectTrigger time outand set it to5。

The figure shows the updated tool settings.

ClickCapture Data。The data capture IP captures 1024 samples when it detects the trigger condition in trigger stage 2 within 5 clock cycles, preceded by the trigger condition detected in trigger stage 1.