法拉第加速SIP开发，并收缩NAND闪光控制器ECC发动机门数57％，基于模型的设计

Challenge

Accelerate the development of SoCs and ASICs

Solution

使用MathWorks工具进行基于模型的设计，加快系统级模拟，提高系统性能，缩短上市时间

Results

Simulations 200 times faster
吞吐量性能增加了15％
Gate count cut by 57%

“The Simulink environment is ideal for system-level architecture exploration. The simulations are 200 times faster than they were in our previous workflow—and Simulink models can be easily converted to C as well as to HDL code, which enables high scalability and reusability.”
Ken Chen, Faraday

Faraday’s silicon IP on an SoC.

Many integrated circuit manufacturers rely on silicon intellectual property (SIP) providers for system-on-a-chip (SoC) and application-specific integrated circuit (ASIC) design. For SIP designers, memory controllers represent an opportunity and a challenge: an opportunity because every microprocessor subsystem needs a memory controller; a challenge because memory controllers are complex designs that need continual enhancements to support a wide array of memory devices. SIP providers like Faraday Technology Corporation gain a competitive advantage if they reduce the gate count of their designs and shorten the development cycle for memory controllers and other modules, which ultimately lowers costs for their customers.

法拉第采用了基于模型的设计的Mathworks工具，以加速SIP开发，探索系统级设计替代品，并改善工程师之间的沟通。

“金宝appSimulink是一个很好的集成，模拟和探索设计架构的环境，”法拉第ESL方法经理Ken Chen说。“通过Sim金宝appulink，我们可以比RTL模拟快速执行基于周期的模拟，这使我们能够快速识别最佳设计配置，并将产品更快地获得产品。”下载188bet金宝搏

Stateflow chart of the error correcting code (ECC) engine for Faraday’s NAND flash controller.

Challenge

In Faraday’s development workflow, engineers create design modules that they can rapidly configure and assemble into integrated system-level models. In the past, these modules were hand coded in SystemC, C++, or Verilog^®。When memory controller standards changed, the modules had to be recoded. Not only did hand coding take time, but the modules often had to be ported into another language for RTL simulation on proprietary simulation platforms.

当法拉第的模块包括离散时间相互作用时，模拟本身很慢。例如，控制双数据速率（DDR）存储器或闪存数据流量的模块必须采用复杂的通信协议，并管理大量数据。模拟这些模块证明这么缓慢，以满足他们的截止日期，法拉第不得不限制设计迭代和测试。对于优化的时间很少，工程师专为最糟糕的情况而设计，它导致了更廉价的设计，以及更高的成本 - 比必要的成本更高。

Plots of system performance under various conditions

各种条件下系统性能的曲线。更快的模拟使得Faraday能够执行更多的设计迭代并实现更好的系统优化和性能。

Solution

法拉第工程师建立了新的工作流程，他们使用Matlab^®, Simulink^®, and Stateflow^®要模拟和模拟其系统级设计和Simulink Coder™和HDL Coder™以从其型号生成代码。金宝app

Working in Simulink and Stateflow, the engineers modeled multiple design modules, including finite state machines (FSMs) for the DDR and flash controllers. They performed extensive simulations in Simulink to ensure that the models were cycle accurate for a range of configurations. They used MATLAB to run statistical analysis on the models.

In the architecture design phase, Faraday engineers evaluated various combinations of modules and tried different parameter values. They used their simulation results to optimize and improve the designs. “Stateflow makes it easy for engineers to communicate complex controller designs in detail and at a level of abstraction that is easy to understand,” says Chen.

As a faster alternative to RTL simulation, Faraday engineers used Simulink Coder to generate C code from their model. This C code provides a programmer’s view of the design and can be integrated into many virtual platform solutions for software development and system-level architecture exploration.

在实施阶段，而不是手动编码其设计，法拉第工程师使用HDL编码器从相同的Simulink模型自动生成HDL代码，以集成到其RTL仿真中。金宝app此工作流使得Faraday能够缩短其从架构设计移动到基于FPGA的原型的设计过程。

Faraday has completed the DDR and flash controller projects and delivered the SIP designs to their customer on schedule. The engineering team is positioned to accelerate development on future memory controller projects by reusing and adapting their existing models.

Results of gate count optimization. By exploring system performance under various conditions, Faraday engineers met performance requirements and removed redundant elements to optimize gate count.

Results

Simulations 200 times faster。使用Simulink和StateFlow的系统级模型的模拟比比较的RTL模拟快2金宝app00倍。因此，法拉第完成了更多的设计迭代并快速识别出最佳参数和配置。

吞吐量性能增加了15％。Simulink simulations revealed inefficiencies in the legacy design—specifically, in the arbiter and FIFO mechanism. Instead of redesigning the entire system, Faraday engineers focused on these components, quickly increasing throughput by 15%. By using Model-Based Design for the new DDR controller, Faraday improved system performance by more than 33%.

Gate count cut by 57%。在过去，缓慢模拟和严格的时间表有限的设计迭代，并强迫法拉第仅供最坏情况的情况设计。使用MATLAB，SIMUL金宝appINK和StateFlow，它们在标称和最坏情况场景下应用了统计错误模型和评估系统性能。然后，他们可以提出知情的权衡决策，将整体门数减少57％。

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