This output port indicates the current capture window. The value of this output port is an integer from 1 to the value of theSample depthparameter.

This output port indicates the position of the trigger detection clock cycle within a capture buffer.

The block returns one frame of data per time step, where the frame is the entire capture buffer for each signal. Each frame containsSample depthvalues, as specified at generation time. The default sample time provides for unbuffering each frame into single samples, which results in a sample time of 1.

This parameter is read-only. It reflects the value you specified at generation time.

Specify the number of recurrences to capture. This value must be a power of two, up toSample depth. Awindow depthis defined asSample depth/Number of capture windows. Consider theNumber of capture windowswhen setting theSample depth, to allow for sufficient buffering.

Specify the number of trigger stages. This value must be an integer from 1 toM, whereMis set by theMax trigger stagesparameter of theFPGA Data Capture Component Generatortool. When you specify theMax trigger stagesparameter, consider the maximum number of trigger stages in which you plan to configure the trigger conditions to capture data.

By default, the clock cycle when the trigger is detected is the first sample of the capture buffer. You can change the relative position of the trigger detection cycle within the capture buffer. A nondefault trigger position means that some samples are captured before the trigger occurs. You can set this parameter to any number between 0 andwindow depth–1, inclusive. When the trigger position is equal to thewindow depth–1, the last sample corresponds to the cycle when the trigger occurs. IfNumber of capture windowsis greater than one, the same trigger position applies to all windows. SeeTriggers.

This parameter is read-only. The signal names you specified at generation time are listed in the drop-down menu at the bottom. Click the+button to add a signal to the trigger condition.

To compare signals, select one of these operators:==,!=,<,>,<=, or>=. To compare signals containingXorx(don't-care value), specify either==or!=operator.

The trigger condition can be composed of value comparisons of one or more signals. This parameter specifies the value to match for each signal.

multi-bit信号,指定一个十进制、二进制、or a hexadecimal value within the range of the data type associated with the signal. While providing hexadecimal or binary values, you can provide values with a combination ofXorx(don't care value) to enable bit masking. While comparing the values, the trigger condition discards place values withXorxand provides the output.

To separate a group of bits for better readability, you can use_between bits. For example, you can represent a 32-bit binary value as0b1010_XXXX_1011_XXXX_1110_XXXX_1111XXXXand a 32-bit hexadecimal value as0xAB_CDEXFX.

Forbooleansignals, select a level or edge condition. SeeTriggers.

This parameter is indicated by the logic gate icon. Click theChange operatorbutton to toggle betweenANDandOR.

The trigger condition can be composed of value comparisons of one or more signals. Combine these value comparisons with only one type of logical operator. Suppose three signals,A,B, andC, make up the trigger condition. The options are:

A == 10 AND B == 'Falling edge' AND C == 0

A == 10 OR B == 'Falling edge' OR C == 0

Within this many data capture IP core clock cycles, the trigger condition must occur in a trigger stage in which you are enabling this parameter. You can specify any integer value from 1 to 65,536 according to your requirements. Select this parameter to enable trigger time out in a trigger stage. A trigger time out is not allowed inTrigger Stage 1.

If a trigger condition is enabled, but the HDL IP core does not detect the condition, the data capture request times out after this many seconds. No data is returned to Simulink.

Select this parameter to enable capture condition logic in the data capture IP core. Enable capture condition logic to use a capture condition to control which data to capture from the FPGA. The data capture IP core evaluates the capture condition at each clock cycle and captures only the data that satisfies the capture condition. For more information on capture conditions, seeCapture Conditions.

Dependencies

To enable this parameter, in theFPGA Data Capture Component Generatortool, selectInclude capture condition logic.

This parameter is read-only. The signal names you specified as triggers at generation time are listed in the drop-down menu at the bottom. Click the+button to add a signal to the capture condition.

Dependencies

To enable this parameter, selectEnable capture condition logic.

To compare signals, select one of these operators:==,!=,<,>,<=, or>=. To compare signals containingXorx(don't-care value), specify either==or!=operator.

Dependencies

To enable this parameter, selectEnable capture condition logic.

The capture condition can be composed of value comparisons of one or more signals. This parameter specifies the value to match for each signal.

multi-bit信号,指定一个十进制、二进制、or a hexadecimal value within the range of the data type associated with the signal. While providing hexadecimal or binary values, you can provide values with a combination ofXorx(don't care value) to enable bit masking. While comparing the values, the capture condition discards place values withXorxand provides the output.

To separate a group of bits for better readability, you can use_between bits. For example, you can represent a 32-bit binary value as0b1010_XXXX_1011_XXXX_1110_XXXX_1111XXXXand a 32-bit hexadecimal value as0xAB_CDEXFX.

Forbooleansignals, select a level or edge condition. SeeCapture Conditions.

Dependencies

To enable this parameter, selectEnable capture condition logic.

This parameter is indicated by the logic gate icon. Click theChange operatorbutton to toggle betweenANDandOR.

The capture condition can be composed of value comparisons of one or more signals. Combine these value comparisons with only one type of logical operator. You cannot mix and match the combination operators. SeeCapture Conditions.

Dependencies

To enable this parameter, selectEnable capture condition logic.

This parameter is read-only. It reflects the name of theCapture_Windowoutput port, the name of theTrigger_Positionoutput port, and the signal names you specify at generation time.

This parameter is read-only. It reflects the value you specified at generation time.

TheData Typemenu provides data type suggestions that match the bit width of the captured signal. This size is the width you specified for the port on the generated IP. You can type in this field to specify a custom data type. If the signal is 8, 16, or 32 bits, the default isuint. If the signal has one bit, the default isboolean. If the signal is a different width, the default isnumerictype(0,bitWidth,0).

Name of the JTAG cable used for data capture, specified as a character vector. Use this parameter when the board is connected to two JTAG cables of the same type.

Dependencies

To enable this parameter, in theFPGA Data Capture Component Generatortool, set theConnection typeparameter toJTAG.

Specify this parameter if more than one JTAG cable is connected to the host computer. When not specified, theFPGA Data Readerblock will auto-detect the JTAG cable type, in the following order:

Dependencies

To enable this parameter, in theFPGA Data Capture Component Generatortool, set theConnection typeparameter toJTAG.

Position of the FPGA in the JTAG scan chain, specified as a positive integer.

Dependencies

To enable this parameter, in theFPGA Data Capture Component Generatortool, set theConnection typeparameter toJTAG.

Number of instruction register lengths before the FPGA, specified as a nonnegative integer.

Dependencies

To enable this parameter, in theFPGA Data Capture Component Generatortool, set theConnection typeparameter toJTAG.

Number of instruction register lengths after the FPGA, specified as a nonnegative integer.

Dependencies

To enable this parameter, in theFPGA Data Capture Component Generatortool, set theConnection typeparameter toJTAG.

在MH指定JTAG时钟频率z. For Xilinx^®FPGAs, the JTAG clock frequency is 33 or 66 MHz. The JTAG frequency depends on the type of cable and the maximum clock frequency supported by the FPGA board.

Dependencies

To enable this parameter, in theFPGA Data Capture Component Generatortool, set theConnection typeparameter toJTAG.

Specify the internet protocol (IP) address of the Ethernet port on the FPGA board as a dotted-quad value. The device IP address must be a set of four numbers consisting of integers in the range from 0 to 255 that are separated by three dots.

Dependencies

To enable this parameter, in theFPGA Data Capture Component Generatortool, set theConnection typeparameter toEthernet.

Specify the user datagram protocol (UDP) port number of the FPGA board as an integer from 255 to 65,535.

Dependencies

To enable this parameter, in theFPGA Data Capture Component Generatortool, set theConnection typeparameter toEthernet.