Introduction

ADS-B is an air traffic management and control surveillance system. The broadcast messages (approximately once per second) contain the flight information including position and velocity. For introduction on ADS-B technology and modes of transmission, see [1]. TheHDLRxsubsystem is optimized for HDL code generation. The captured received signal is streamed into the receiver (HDLRxsubsystem) front end. The streaming output of the receiver is buffered and passed to theMapResultsMATLAB® function to view the output.

Structure of the Example

The model supports both Normal and Accelerator modes. The top-level structure of the ADS-B receiver model is shown in the following figure.

The receiver input data is captured usingHW/SW Co-Design Implementation of ADS-B Receiver Using Analog Devices AD9361/AD9364(Communications Toolbox Support Package for Xilinx Zynq-Based Radio)running on the Zynq® platform. The captured data represents the baseband received signal with a sampling rate of 4 MHz. The data contains 8 frames of extended squitter messages. The ADS-B transmitter modulates the 112-bit extended squitter messages using 2-bit pulse-position modulation, and adds a 16-bit prefix. Then, to generate 4 MHz data, each 240-bit message is zero-padded and upsampled by 2.

This diagram shows the detailed structure of theHDLRxsubsystem.

The subsystems listed here are described further in the following sections.

1.Magnitude Calculation- Finds the complex modulus of the received input signal

2.Threshold Calculation- Calculates the threshold value based on received input signal strength

3.Correlation with Preamble- Correlates the received signal with reference signal to detect the preamble

4.Timing Control- Provides timing synchronization for the receiver

5.Bit Process- Decodes symbols using PPM demodulation

6.Compute CRC and Frame Validation- Validates the frame by checking for CRC errors

HDL Optimized ADS-B Receiver

1.Magnitude Calculation

The inputs to theMagnitude Calculationsubsystem are the in-phase (real) and quadrature (imaginary) phase samples. This subsystem outputs the modulus of the complex number. The sqrt(I^2+Q^2) can be approximated by the "|L|+0.4*|S| algorithm" described on page 238 of [2].

where

|L| is the larger value of |I| or |Q|

|S| is the smaller value of |I| or |Q|.

The Gain block converts received input from 12-bit to 16-bit word length.

For the implementation of "|L|+0.4|S| algorithm", see the following model.

2.Threshold Calculation

TheThreshold Calculationsubsystem calculates the signal energy and applies a scaling factor to create a threshold for preamble detection. Moving Average Filter is a serial FIR filter architecture with 32 coefficients that operates on the magnitude values. The coefficients of the FIR filter are selected to find the average energy of the received signal. This example scales the signal energy by 5 to detect valid ADS-B preambles. For details on FIR filter, seeDiscrete FIR Filter(Simulink).

3.Correlation with Preamble

TheCorrelation with Preamble子系统的接收信号相关ADS-B reference/preamble sequence [1 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0] using a peak detection filter. The peak detection filter is a serial FIR Filter architecture, configured with coefficients that match the preamble sequence. Preamble correlation identifies potential ADS-B transmissions and aligns our bit detection algorithm with the first message bit. The preamble is detected if the peak amplitude exceeds the scaled threshold value. Once the preamble is detected, the correlation value is passed on as input(SyncCorr) to theTiming Controlblock.

4.Timing Control

TheTiming Controlblock is a state machine that detects the preamble and generates the control signals ActivateBP and Reset, that indicate the start of frame, end of frame and reset status to theBit ProcessandCompute CRC and Frame Validationblocks.

5.Bit Process

TheBit Processsubsystem demodulates and down converts the 4 MHz received signal to a 1 MHz bit sequence. Each data bit is represented by four PPM bits. To demodulate, the block finds the sum of the first two bits and the last two bits of each quadruplet. Then, it compares the sums to determine the original bit value. The output valid signal is asserted every fourth cycle to align with 1 MHz bit sequence.

6.Compute CRC and Frame Validation

This subsystem checks for mismatches in the 24-bit checksum of each 88-bit message. The CRC block needs an indication of the frame boundaries to determine which bits are the checksum. The rising edge of the ActivateBP signal generated from theTiming Controlblock indicates the start of frame, and the falling edge indicates the end of the frame. The start signal is delayed to match the demod latency. When the block output err signal is zero, the frame is a valid ADS-B message. The subsystem buffers the message bits until the message is confirmed to have no CRC error.

Launch Map and Log Data

You can launch the map and start text file logging using the two slider switches (Launch Map and Data Logging).

Launch Map- Launch the map where the tracked flights can be viewed.NOTE:You must have a Mapping Toolbox™ license to use this feature.

Data Logging- Save the captured data in a TXT file. You can use the saved data for later for post processing.

Results and Displays

TheHDLRxsubsystem demodulates and decodes the ADS-B data and the output is streamed throughDeserializer1Dblock andMapResultsMATLAB function, which produces hexadecimal output information about the aircraft. Each extended squitter Mode S packet contains partial information (any of Aircraft ID, Flight ID, Altitude, Speed, and Location) about the aircraft and the table is built up from multiple messages. The output is obtained as shown in the following diagram. The packet statistics include the number of detected packets, the number of correctly decoded packets, and packet error rate (PER). These aircraft details match the transmitted values from theHW/SW Co-Design Implementation of ADS-B Receiver Using Analog Devices AD9361/AD9364(Communications Toolbox Support Package for Xilinx Zynq-Based Radio)example.

HDL Code Generation and Synthesis Results

Pipeline registers have been added to the model to make sure thatHDLRxsubsystem does not have a long critical path. The HDL code generated from theHDLRxsubsystem was synthesized using Xilinx® Vivado® on aZynqFPGA with the device 7z045ffg900-2, and the design achieves264.2 MHzclock frequency, which is sufficient to decode the real-time ADS-B signals. The generated HDL code is tested and verified in the real-time exampleHW/SW Co-Design Implementation of ADS-B Receiver Using Analog Devices AD9361/AD9364(Communications Toolbox Support Package for Xilinx Zynq-Based Radio). To check and generate the HDL code referenced in this example, you must have an HDL Coder™ license. The following table shows the synthesis results of this example.

You can use the commands makehdl and makehdltb to generate HDL code and a test bench for the HDLRx subsystem. To generate the HDL code, use the following command:

makehdl('commadsbrxhdl/HDLRx')

To generate a test bench, use the following command:

makehdltb('commadsbrxhdl/HDLRx')

References