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GSM Digital Down Converter in Simulink

此示例显示了如何模拟GSM(移动)基带转换的定点数字下转换器的稳态行为。该示例模型使用Simulink®和DSP System Toolbox金宝app™的块来模拟TI GC4016四Quad数字下转换器(DDC)的操作。

DDC执行:

  • 输入信号的数字混合(向下转换)

  • Narrow band low-pass filtering and decimation

  • Gain adjustment and final resampling of the data stream

In this model, the DDC accepts a high sample-rate (69.333 MSPS) bandpass signal. The DDC produces a low sample-rate (270.83 KSPS) baseband signal, ready for demodulation.

更改GSM源

You can switch between a chirp and a sinusoid signal using theGSM源block in the example model. You can replace this block with a different source to model your application, however you will have to adjust the parameters of the downstream mixer subsystems.

调整归一化调谐频率和相位偏移值

To assure that your GSM source signal gets received and mixed down with minimum error, you should adjust the规范化的调谐频率寄存器的值andNormalized Phase Offset Register Value

由于此示例正在模拟Ti GC4016四数字下转换器,因此必须以特定格式输入这些值。这规范化的调谐频率寄存器的值should be a signed twos-complement 32-bit integer, representing a normalized range between 0 and the sampling frequency. Use positive frequency values for down conversion. TheNormalized Phase Offset Register Valueshould be an unsigned 16-bit integer, also representing a normalized range. For more details, please refer to the TI GC4016 Quad Digital Down Converter documentation and the DSP System ToolboxNCO库块参考文档。

比较基于NCO的基于NCO和基于电源的混合器实现

View the Digital Mixer Real Output scope and Mixer Output Comparison scope to compare the NCO-based Mixer implementation outputs to the CORDIC-based Mixer implementation outputs. Both implementations can be made to produce similar output values, however the implementation choice is based largely on available hardware resources and performance constraints. In general, NCO-based approaches trade off lookup table size (read-only memory resources) with speed performance, whereas CORDIC-based approaches may trade off speed performance for smaller memory resources, based on the number of CORDIC kernel iterations needed.

调整基于NCO的搅拌机参数

Look at the output of the NCO Cosine Spectrum Analyzer block to observe the effects of tuning NCO-based Mixer subsystem block parameters.

抖动

为了在整个可用带宽中传播虚假频率,您可以在累加器相值中添加抖动信号。在此示例中,抖动信号是由PN序列发生器生成的,该PN序列发生器组成二进制移位寄存器和独家或门(NCO块内部)。抖动位的数量自动确定

抖动位的数量=累加器单词长度 - 表地址单词长度长度

当您将抖动位的数量增加到最佳值之外时,噪声底部开始上升。当您将抖动位的数量降低到最佳值以下时,伪频率的出现将减少NCO系统的虚假自由动态范围。

For more information, please see the DSP System ToolboxNCO库块参考文档。

调整基于电源的搅拌机参数

Look at the output of the CORDIC Cosine Spectrum Analyzer block to observe the effects of tuning CORDIC-based Mixer subsystem block parameters.

带有抖动发电机的相位累加器

带有抖动发电机子系统的相位累加器计算角度Theta脐带复合物旋转函数的输入。查看电源余弦谱分析仪块的输出,以观察使用抖动发生器子系统参数调整相累加器的效果。

As in the NCO-based Mixer described above, you can add a dither signal to the phase accumulator values to spread the spurious frequencies throughout the available bandwidth. The dither signal is generated by a PN Sequence Generator consisting of binary shift registers and exclusive-or gates (internal to the Phase Accumulator with Dither Generator). The number of dither bits was chosen to be 15 to closely match the cosine spectrum performance of the NCO-based Mixer.

脐带络合物旋转

这脐带络合物旋转computesu * exp(j*theta)using a CORDIC rotation algorithm. Refer to the Fixed-Point Designer™ documentation to learn about theCORDICROTATE函数。艾尔so please refer to the references listed below for more information on using CORDIC-based digital mixer approaches.

调整分解过滤器参数

这CIC Decimator, Compensation FIR, and Programmable FIR blocks are used together to achieve:

  • A high decimation ratio

  • 艾尔iasing attenuation

  • 特定于应用程序的过滤

You can use Filter Designer to visualize and analyze the filters. Refer to the Signal Processing Toolbox™ documentation to learn about Filter Designer.

Double-clicking on the CIC Decimator block in the example model lets you see the implementation of the filter. To customize the DDC, you can change the CIC filter by editing the CIC Decimation block parameters.

CIC Decimation filters are implemented using integer overflow "wrap" arithmetic to perform the decimation filtering within their cascaded integrator-comb structures. This type of filter is economical for implementation on hardware such as FPGAs and ASICs, because the only arithmetic operation required is summing; no multiplies are required. For more information on CIC filters please refer to the references below.

这Compensation FIR block adjusts for roll-off of the CIC passband, and the Programmable FIR block filters the signal to meet the requirements of the GSM baseband spectral mask. You can adjust the gain and coefficients of these filters.

这input gain to Compensation FIR filter is set through the增益参数。Ti GC4016四QUAD数字下转换器需要从一个参数将CIC过滤器的输出移动0-7位2^COARSE。Thus, you may enter 0 - 7 for the在粗增益块蒙版中获得参数。

这gain at the output of the Programmable FIR block is set through theFINE增益参数。Ti GC4016四QUAD数字下转换器需要从一个FINEparameter to shift the signal by 1 - 4 bits, according toFINE/1024。Thus, you may enter116383for theFINEgain parameter in the Fine Gain block mask.

调整速率转换块参数

This final stage of the DDC can be used to change the rate of the output of the DDC to match the baseband frequency of your particular system's demodulator input. The Rate Conversion block is a fixed-point filter that acts similarly to the FIR Rate Conversion block in the DSP System Toolbox. The Rate Conversion block'sNDELAY参数是插值因子,并且NDEC参数是分解因子。

Analyzing the DDC

您可以使用示波器和定点工具来观察和分析模拟的结果。

Scopes

Double-click on the Scopes block in the example model to gain access to the following scopes:

  • NCO Cosine Spectrum

  • 脐带余弦

  • 数字搅拌机真实输出

  • 混音器输出比较

  • CIC Decimator Output

  • 补偿FIR输出

  • Programmable FIR Output

  • 重采样器输出

定点工具

通过转到分析菜单并选择定点工具来调用示例的定点工具接口。该接口使您可以在示例模型中任何子系统中的定点块中查看最大值,最小值和溢出。有关固定点工具的更多信息,金宝app请参阅Simulink和Ridepoint Designer™文档。

References

[1] Hogenauer,E。B.,“用于拆卸和插值的数字过滤器的经济类别,”IEEE®交易有关声学,语音和信号处理的交易,ASSP -29(2):155-162,1981。

[2] Lohning, M., Hentschel, T., and Fettweis, G., "Digital Down Conversion in Software Radio Terminals",Proceedings of the Tenth European Signal Processing Conference (EUSIPCO),1517-1520,2000。

[3] Valss, J., Sansaloni, T., Perez-Pascual, A., Torres, V., and Almenar, V., "The Use of CORDIC in Software Defined Radios: A Tutorial",IEEE通讯杂志, 46 - 50, September 2006.

[4] Yang,S.,Wu,Z。和Ren,G。,“基于数字接收器的基于FPGA的FSK的设计和实施”,1st International Symposium on Systems and Control in Aerospace and Astronautics (ISSCAA),819-821,2006年1月。

[5] Andraka,Ray,“基于FPGA的计算机的Cordic算法调查”,1998年ACM/SIGDA第六届国际田间可编程门阵列的会议论文集, 191 - 200, Feb. 22-24, 1998.

[6] Volder, Jack E., "The CORDIC Trigonometric Computing Technique",IRE Transactions on Electronic Computers, Volume EC-8, 330 - 334, September 1959.