Customize Black Box or HDL Cosimulation Interface

You can customize port names and set attributes of the external component when you generate an interface from the following blocks:

Modelwith black box implementation
Subsystemwith black box implementation
HDL Cosimulation

Interface Parameters

Open the HDL Block Properties dialog box to see the interface generation parameters.

The following table summarizes the names, value settings, and purpose of the interface generation parameters.

Note

You cannot specify clock, reset, and clock enable signals explicitly in your Simulink^®model by using theAddClockEnablePort,AddClockPort, andAddResetPortparameters. Instead, use these parameters to add a clock, reset, or clock enable port in the generated HDL code.

Parameter Name	Values	Description
AddClockEnablePort	`on`\|`off` Default:`on`	If`on`, add a clock enable input port to the interface generated for the block. The name of the port is specified byClockEnableInputPort.
AddClockPort	`on`\|`off` Default:`on`	If`on`, add a clock input port to the interface generated for the block. The name of the port is specified byClockInputPort.
AddResetPort	`on`\|`off` Default:`on`	If`on`, add a reset input port to the interface generated for the block. The name of the port is specified byResetInputPort.
AllowDistributedPipelining	`on`\|`off` Default:`off`	If`on`, allow HDL Coder™ to move registers across the block, from input to output or output to input.
ClockEnableInputPort	Default:`clk_enable`	Specifies HDL name for block's clock enable input port.
ClockInputPort	Default:`clk`	Specifies HDL name for block's clock input signal.
ConstrainedOutputPipeline	Default: 0	Specifies the number of delays that you want the code generator to insert at the output of the interface by redistributing existing delays in your design.
EntityName	Default: Entity name string is derived from the block name, and modified when necessary to generate a legal VHDL^®entity name.	Specifies VHDL`entity`or Verilog^®`module`name generated for the block.
GenericList	Pass a cell array variable that contains cell arrays each with two or three strings, or enter a cell array of cell arrays that each contain two or three strings. The strings represent the name, value, and optional data type of a VHDL`generic`or Verilog`parameter`. The default data type is`integer`. Default: none	Specifies a list of VHDL`generic`or Verilog`parameter`name-value pairs, each with an optional data type specification, to pass to a subsystem with a`BlackBox`implementation. For example, in the HDL Block Properties dialog box, enter`{'name','value','type'}`, or, if the data type is`integer`, enter`{'name','value'}`. To set`GenericList`using`hdlset_param`, at the command line, enter: `hdlset_param (blockname,'GenericList','{''name'',''value'',''type''}');` If the data type is`integer`, at the command line, enter: `hdlset_param (blockname,'GenericList','{''name'',''value''}');`
ImplementationLatency	-1 \| 0 \| positive integer Default: -1	Specifies the additional latency of the external component in time steps, relative to the Simulink block. If 0 or greater, this value is used for delay balancing. Your inputs and outputs must operate at the same rate. If -1, latency is unknown. This disables delay balancing.
InlineConfigurations (VHDL only)	`on`\|`off` Default: If this parameter is unspecified, defaults to the value of the global`InlineConfigurations`property.	If`off`, suppress generation of a configuration for the block, and require a user-supplied external configuration.
InputPipeline	Default: 0	Specifies the number of input pipeline stages (pipeline depth) in the generated code.
OutputPipeline	Default: 0	Specifies the number of output pipeline stages (pipeline depth) in the generated code.
ResetInputPort	Default:`reset`	Specifies HDL name for block's reset input.
VHDLArchitectureName (VHDL only)	Default:`rtl`	Specifies RTL architecture name generated for the block. The architecture name is generated only ifInlineConfigurationsis`on`.
VHDLComponentLibrary (VHDL only)	Default:`work`	Specifies the library from which to load the VHDL component.

Customize Black Box or HDL Cosimulation Interface

Interface Parameters

Related Topics

HDL Coder Documentation

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