主要内容

生成一个IP核心ZynqPlatform from金宝app

Generate an IP Core

To generate a custom IP core to target a platform supported by theHDL Coder™ Support Package for Xilinx®Zynq®Platform:

  1. 打开HDL工作流顾问。

  2. 在里面设定目标>设置目标设备和合成工具任务，用于Target workflow, selectIP Core Generation.

    HDL编码器自动设置Synthesis tooltoXilinx Vivado, but you can change theSynthesis tooltoxilinx ise.

  3. For目标平台, select one of these options:

    • Xilinx Versal AI Core Series VCK190 Evaluation Kit

    • Xilinx Zynq Ultrascale+ MPSoC ZCU102 Evaluation Kit

    • Xilinx Zynq ZC702 evaluation kit

    • Xilinx Zynq ZC706 evaluation kit

    • Zedboard

    ClickRun This Task.

    If you do not see your target hardware in the dropdown menu, select获得更多下载目标支持包。金宝app

  4. 在里面设定目标>设定目标Interface任务：

    • Reference design和Reference design path：如果您有下载的参考设计，请选择您的Reference design. ForReference design path, enter the path to your downloaded reference design components.

    • Target Platform Interface: Select an interface for each port, then clickApply.

      You can map each DUT port to one of the following interfaces:

      • Axi4-Lite: Use this slave interface to access control registers or for lightweight data transfer. HDL Coder generates memory-mapped registers and allocates address offsets for the ports you map to this interface.

      • AXI4: Use this slave interface to connect to components that support burst data transmission. HDL Coder generates memory-mapped registers and allocates address offsets for the ports you map to this interface.

      • AXI4-Stream Video: Use this interface to send or receive a 32-bit scalar video data stream.

      • External Port：使用外部端口连接到FPGA外部IO引脚或其他具有外部端口的IP内核。

        To connect to FPGA external IO pins, forBit Range / Address / FPGA Pin，输入销钉名称的单元格数组。如果您不以单元格式格式输入销钉名称，则在嵌入式系统工具项目中将外部端口无连接。例如，您可以输入：{'Y10', 'A10', 'B10', 'D10'}.

      • A board-specific interface, such asLED通用目的,倾角开关,Push Buttons L-R-U-D-S,Pmod Connector JA1,Pmod Connector JB1,Pmod Connector JC1, orPmod Connector JD1. Use these external ports to connect to external IO pins on the FPGA board.

        在生成的IP核心中，这些端口是通用外部端口。在稍后的步骤中，如果您使用HDL Workflow Advisor将生成的IP核心与嵌入式软件在嵌入式系统工具项目中集成在一起，则编码器将这些端口连接到特定于董事会的FPGA引脚。

  5. 在里面HDL Code Generation>Generate RTL Code and IP Core任务：

    • IP核心文件夹: HDL Coder generates the IP core files in the output folder shown, including the HTML documentation.

    • IP repository: If you have an IP repository folder, enter its path manually or by using the浏览按钮。The coder copies the generated IP core into the IP repository folder.

    • 其他源文件: If you are using a black box interface in your design to include existing Verilog®or VHDL®code, enter the file names. Enter each file name manually, separated with a semicolon (;), or by using theAdd按钮。源文件语言必须匹配您的目标语言。

    • Generate IP core report：启用此选项可以为IP核心生成HTML文档。

  6. If you want to set options in the other HDL Workflow Advisor tasks, set them.

  7. Right-click theHDL Code Generation>Generate RTL Code and IP Core任务并选择运行到选定的任务.

    To view the IP core report, click the link in the message window.

To learn more about custom IP core generation, see自定义IP核心生成.

Requirements and Limitations

生成自定义IP核心：

  • DUT必须是一个原子系统。

  • There cannot be both an AXI4 interface and AXI4-Lite interface in the same IP core.

  • The DUT cannot contain Xilinx System Generator blocks.

  • If your target language is VHDL, and your synthesis tool is Xilinx ISE, the DUT cannot contain a model reference.

To map your DUT ports to an AXI4-Lite interface, the input and output ports must:

  • 宽度小于或等于32位。

  • Be scalar.

将DUT端口映射到AXI4-stream视频接口时，适用以下要求和限制：

  • Ports must have a 32-bit width.

  • Ports must be scalar.

  • The model must be single rate.

  • 您最多可以拥有一个输入视频端口和一个输出视频端口。

  • Your synthesis tool must be Xilinx ISE.

The AXI4-Stream Video interface is not supported in协调性 - 阻止处理器/FPGA同步模式。