Frame Conversion

(Removed) Specify sampling mode of output signal

TheFrame Conversionblock has been removed.

Library

Signal Management / Signal Attributes

dspsigattribs

Description

The Frame Conversion block passes the input through to the output and sets the output sampling mode to the value of theSampling mode of output signalparameter, which can be eitherFrame-basedorSample-based. The output sampling mode can also be inherited from the signal at the Ref (reference) input port, which you make visible by selecting theInherit output sampling mode from input portcheck box.

The Frame Conversion block does not make any changes to the input signal other than the sampling mode. In particular, the block does not rebuffer or resize 2-D inputs. Because 1-D vectors cannot be frame based, when the input is a length-M1-D vector and the block is inFrame-basedmode, the output is a frame-basedM-by-1 matrix — that is, a single channel.

Parameters

Inherit output sampling mode from input port: 选择启用裁判端口的块inherits the output sampling mode.
Sampling mode of output signal: Specify the sampling mode of the output signal,Frame-basedorSample-based.

Supported Data Types

Port	Supported Data Types
In	Double-precision floating point Single-precision floating point Fixed point (signed only) Boolean 8-, 16-, and 32-bit signed integers 8-, 16-, and 32-bit unsigned integers Enumerated
Ref	Double-precision floating point Single-precision floating point Fixed point (signed only) Boolean 8-, 16-, and 32-bit signed integers 8-, 16-, and 32-bit unsigned integers Enumerated
Output	Double-precision floating point Single-precision floating point Fixed point (signed only) Boolean 8-, 16-, and 32-bit signed integers 8-, 16-, and 32-bit unsigned integers Enumerated

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is`0`. For more details, seeConstrainedOutputPipeline(HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is`0`. For more details, seeInputPipeline(HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is`0`. For more details, seeOutputPipeline(HDL Coder).

Complex Data Support

This block supports code generation for complex signals.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced before R2006a

Buffer	DSP System Toolbox
Check Signal Attributes	DSP System Toolbox
Convert 1-D to 2-D	DSP System Toolbox
Convert 2-D to 1-D	DSP System Toolbox
Inherit Complexity	DSP System Toolbox
Unbuffer	DSP System Toolbox
Probe(Simulink)	金宝app
Reshape(Simulink)	金宝app
Signal Specification(Simulink)	金宝app