Outline of the Example

Requirements and Prerequisites

对于Cosimulation和FPGA-In-in-Loop，您需要以下软件和硬件：

MATLAB® and FPGA design software can either be locally installed on your computer or on a network accessible device. If you use software from the network you will need a second network adapter installed in your computer to provide a private network to the FPGA development board. Consult the hardware and networking guides for your computer to learn how to install the network adapter.

Note: The example includes code generation. If you do not have access to HDL Coder software you can skip the code generation step in this example and use the HDL files provided for you together with the FIL wizard to simulate them with FPGA-in-the-loop.

Create a Reference Model for the Finite State Machine

参考模型是实现的行为的仿真模型。它通常用于HDL验证，通过将其与RTL实现实例化，给出与两者的相同输入并进行比较它们的输出。验证中的参考模型的优点是它们可以独立于实现（通常由不同的人）开发，提供了对预期行为的独立验证，它们比实际实现更容易（不需要合成或实际设备时序））它们通常在模拟中快速运行。

验证此示例中的传统HDL代码的第一步是为该部分的设计创建参考模型。已经为FSM完成了这一点。打开行为_mimo.slx模型。双击MIMO解码器子系统，您可以看到FSM子系统包含一个实现FSM行为的MATLAB功能块。此参考模型将用于验证FSM的传统HDL代码。

1. Use Cosimulation Wizard to Import Legacy HDL Code

Invoke the cosimulation wizard by typing the following at the MATLAB command prompt:

cosimWizard

Select HDL cosimulation with Simulink and your preferred HDL simulator from the drop-down list. If the HDL simulator is not on your system path, provide the path and click Next.

Add FSMSubsystem.vhd, FSMSubsystem_pkg.vhd, and Embedded_Controller.vhd files (located in the "verify_legacy_hdlsrc" folder) using the cosimWizard's Add button and reorder the list to place FSMSubsystem.vhd at the bottom and FSMSubsystem_pkg.vhd at the top of the list, for correct compilation ordering. Then click Next.

单击以下2面板上的“下一步”以接受默认值并到达输入/输出端口面板。在输入端口列表中，从前3个端口的下拉列表中选择以下端口类型值：

clk : Port Type = clock reset : Port Type = reset clk_enable : Port Type = reset

This identification of Port Types causes the cosimulation block to force those signals in the HDL simulator rather than require that they be driven in the Simulink diagram. In this example we treat the clk_enable port as another reset for cosimulation. Before you proceed to the next step similarly select "unused" for the ce_out, causing it to be omitted from the cosimulation block since it is not needed in Simulink.

我cosimulation向导自动识别nputs and outputs in the HDL code and creates the cosimulation block for Simulink based on the ports it finds there. There are some details about the output ports that it cannot learn from the HDL code. In the HDL code the outputs are simply collections of bits with no indication of how you would like to interpret those bits in Simulink. You have to tell the cosimulation wizard whether you want those bits to be seen as signed or unsigned values and, if they are to be interpreted as fixed-point numbers, where to put the radix point.

In the Output Port Details panel refine the data type for each output. In the case of this design the output ports are to be interpreted as follows. Note that there are multiple scalar ports in the HDL code for the vector ports (out_1, out_6, out_9, out_10, out_11, out_12):

OUT_1：签名，分数长度= 0（4个标量端口）OUT_2：无符号，分数长度= 0 OUT_3：无符号，分数长度= 0 OUT_4：unsigned，分数长度= 0 OUT_5：签名，分数长度= 10 out_6：签名，分数长度= 10（3个标量）OUT_7：签名，分数长度= 2 OUT_8：未签名，分数长度= 0 OUT_9：签名，分数长度= 0（4个标量端口）OUT_10：签名，分数长度= 0（4个标量）OUT_11：签名，分数长度= 10（4个标量）OUT_12：签名，分数长度= 10（4个标量）OUT_13：无符号，分数长度= 0 OUT_14：签名，分数长度= 0

On the Clock/Reset Details panel set the following values:

CLK周期= 10 ns，主动边缘=上升复位初始值= 1，持续时间= 27 ns clk_enable初始值= 0，持续时间= 37 ns

Click Next to proceed to the Start Time Alignment panel and set the "HDL time to start cosimulation (ns)" to 40.

继续执行最后一步并取消选中“自动确定仿真开始时的时间尺度”复选框。对于这个例子，我们知道Cosimulation的时间尺度应该是1秒，在Simulink中对应于HDL模拟器中的10 ns。金宝app有关使用其他设计的自动时间尺度设置功能的信息，请参阅HDL验证程序文档。设置上述时间尺度，然后单击“完成”。

The cosimulation block will be generated for importing the legacy HDL code into the Simulink model. You can drag and drop the newly generated cosimulation block and the 2 convenience command blocks into the Simulink model, inside the FSMSubsystem block and connect it to the output ports of the FSMSubsystem. A cosimulation model, with comparators and assertion blocks inside the MIMO Decoder subsystem, has been provided for this example. The comparators and assertion blocks have been added to alert you to any mismatches between the outputs of the reference model for the Embedded Controller and the legacy HDL implementation.

Use the following command to resize the generated cosimulation block to make it easier to insert it into the cosimulation model:

set_param('无标题/ fsmsubsystem','位置', [0 0 165 852]);

Open the cosim_mimo.slx model. Drag the new block and convenience command blocks created by cosimWizard into the cosimulation model, replacing the placeholder subsystem inside the MIMODecoder subsystem.

2. Cosimulate to Verify the Legacy HDL Code

In your cosimulation model double-click the "Launch HDL Simulator" block to launch your chosen HDL simulator. Click the Play button in Simulink to start the cosimulation and observe that warning messages are displayed in the MATLAB window. These are indicating mismatches on the output signals because of a discrepancy between the reference FSM model and the HDL implementation.

Now you can use Simulink and HDL simulator debugging features to isolate the problem and fix the bug. In this case the errors arise because a state transition arc was missed in the HDL implementation. Notice in the HDL simulator's waveform display that the FSM state gets stuck very early in the simulation.

Fix the Hand-Written HDL Code and Rerun the Cosimulation

The corrected HDL code has been supplied for this example. Use the following command to copy the new code to your working directory, overwriting the bad version of Embedded_Controller.vhd:

copyfile(fullfile('verify_legacy_hdlsrc','fixed_hdl','embedded_controller.vhd'),'verify_legacy_hdlsrc','f');

Recompile the Legacy HDL code by double-clicking the "Compile HDL Design" block. Exit the HDL simulator if it is still open following the previous execution of the cosimulation and relaunch the HDL simulator, then replay the cosimulation. You should observe no mismatches this time.

既然您已调试并验证了嵌入式控制器的传统HDL代码，您可以继续验证具有FPGA-IN--IN--IN--IN-LOOP的整个MimodeCoder。

Set FPGA Design Software Environment

在使用FPGA循环之前，请确保正确设置系统环境以访问FPGA设计软件。您可以使用该功能hdlsetuptoolpathto add FPGA design software to the system path for the current MATLAB session.

Prepare the Model for HDL Code Generation

To prepare the model for FPGA-in-the-loop incorporating the legacy HDL code and generating new HDL code for the remainder of the MIMO Decoder you need to do 2 things to complete the FPGA implementation:

If you want to follow all steps to prepare the model for HDL code generation using the HDL Blackbox, save the cosimulation model with a different name and proceed with the rest of model preparation as follows:

1. edit the cosimulation model to remove the FSM reference design

2.使用HDL编码器BlackBox将传统HDL合并到模型中进行代码生成

3. rerun the simulation to update the diagram.

3. Generate HDL Code and FPGA-in-the-Loop

This step requires HDL Coder. If you do not have this software, you can use pre-generated HDL files for FIL simulation. Jump directly to step 5. FIL Simulation Using filWizard.

If you want to follow the process to generate the HDL files yourself return to the top level of the model, right click on the MIMODecoder subsystem and under "HDL Code" launch the HDL Coder Workflow Advisor.

The result will be an FPGA programming file for FPGA-in-the-loop simulation of the MIMO Decoder subsystem and a new model containing the original model (including the legacy HDL for the FSM) of the decoder alongside the FPGA-in-the-loop block. It will also have comparators with assertion blocks to identify mismatching signals similar to those we saw in the cosimulation model.

4. Verify the Design with FPGA-in-the-Loop Simulation

Since the generated verification model includes the cosimulation for the FSMSubsystem you will need to use the HDL simulator to run the entire FIL model. Make sure that the HDL simulator from your previous cosimulation is shut down and relaunch the HDL simulator.

在背包的FPGA-in-the-loop模型ed in Step 3, open the FIL block.

Select "Load" to download the FPGA programming file to the device on your board.

Click Play in the Simulink model to run FPGA-in-the-loop simulation.

Observe the results in the comparison scopes and the ErrorRate Calculation in the model. Your FIL simulation results should exactly match the reference model.

5.费尔Simulation Using FIL Wizard

This step is the alternative to Step 4 for those who do not have HDL Coder software. If you've completed Step 4 you need not continue with this step.

The pre-generated HDL files are located in the "verify_legacy_gen_hdlsrc" folder. You can create the FPGA programming file for FPGA-in-the-loop using the FIL wizard. the FIL wizard will also create a FIL block which you can discard because the FIL model provided for this example already contains the FIL block.

Open the FIL wizard by entering the following command:

filWizard

Observe the results in the comparison scopes and the ErrorRate Calculation in the model. Your FIL simulation results should exactly match the reference model.

This concludes the example of Using HDL Cosimulation and FPGA-in-the-loop to Verify HDL Designs.