Verify HDL Design Using SystemVerilog DPI Test Bench
此示例显示了如何使用SystemVerilog DPI测试工作台进行验证需要大型数据集的HDL代码。
In certain applications, simulation of a large number of samples is required to verify the HDL code generated by HDL Coder™ for your algorithm. For instance, these applications require a large number of samples for algorithm verification:
a) Calculation of radar astronomy frequency channels using a polyphase filter bank.
b) Obtaining the Bit Error Rate (BER) from a Viterbi decoder in a communications system.
c) Pixel-streaming video processing algorithms on high-resolution video.
生成HDL测试工作台来验证这种设计很耗时，因为编码器必须在Simulink®中模拟该模型以捕获测试工作台数据。金宝app
A faster generated test bench alternative is the HDL Verifier™ SystemVerilog DPI test bench. The SystemVerilog DPI test bench does not require a Simulink simulation, so for large data sets it generates a test bench in a shorter time than the HDL test bench.
HDL验证器SystemVerilog DPI Test Bench与Simulink Coder™集成在一起，以带金宝app有直接编程接口（DPI）的SystemVerilog组件中的Simulink系统作为生成的C代码。在DPI-C组件中，生成刺激并应用于C子系统，并应用于Simulink系统的生成的HDL代码。金宝app测试工作台将HDL模拟的输出与DPI-C组件的输出进行比较，以验证HDL设计。
多相过滤库
Polyphase filter bank is a widely used technique to reduce inaccuracy in FFT due to leakage and scalloping losses. Polyphase filter bank produces a flatter response as compared to a normal DFT by suppressing out-of-band signals significantly.
The model is a Polyphase Filter Bank which consists of a filter and an FFT that processes 16 samples at a time. For more information about the polyphase filter bank seeHigh-Throughput Channelizer for FPGA。
modelName ='hdlcoder_dpic_testbench';Open_System（modelName）;
设置模型
The InitFcn callback(Model Properties > Callbacks > InitFcn) sets up the model. In this example, a 512-point FFT with a four tap filter for each band is used. The dsp.Channelizer object is used to generate the coefficients.
The algorithm requires 512 filters (one filter for each band). For a vector input of 16 samples the filter implementation shares 16 filters, 32 times. The input data consists of two sine waves, 200KHz and 250 KHz.
生成HDL代码，HDL测试工作台和SystemVerilog DPI测试台
Use a temporary directory for the generated files:
workingDir = tempname;
检查PolyphaseFilterBank子系统是否有HDL代码生成兼容性：
checkhdl('hdlcoder_dpic_testbench/polyphaseFilterBank'，，，，“ TargetDirectory”，WorkingDir）;
Run the following command to generate HDL code:
makehdl（'hdlcoder_dpic_testbench/polyphaseFilterBank'，，，，“ TargetDirectory”，WorkingDir）;
运行以下命令生成测试台：
makehdltb('hdlcoder_dpic_testbench/polyphaseFilterBank'，，，，“ TargetDirectory”，WorkingDir）;
这将通过在Simulink中模拟该模型，然后捕获测试工作台数据来生成HDL测试工作台。金宝app
运行以下命令以生成SystemVerilog DPI测试工作台：
hdlsimulator =“模型”;％支金宝app持的模拟器选项='modelsim'，'cincisive'，'vcs'，'vivado'
makehdltb('hdlcoder_dpic_testbench/polyphaseFilterBank'，，，，“ TargetDirectory”，WorkingDir，“生成vdpitestbench'，，，，HDLSimulator,'generateHdlTestBench'，，，，'离开'）；
This command generates a SystemVerilog test bench without running a Simulink simulation. Instead of a simulation, the code exports the Simulink system as generated C code inside a SystemVerilog component. The test bench verifies the output data by comparing it with the output of the HDL design. The makehdltb function also generates simulator-specific scripts for compilation and simulation.
SystemVerilog DPI测试工作台可用于验证两种目标语言的HDL设计-VHDL®和Verilog®。
Alternatively, you can set SystemVerilog DPI test bench options on the 'HDL Code Generation > Test Bench' pane in Configuration Parameters.
生成的SystemVerilog DPI测试台伪影
When you request a SystemVerilog DPI test bench, the coder generates the following artifacts:
a。）polyphaseFilterBank_dpi_tb.sv-这是验证HDL代码的SystemVerilog测试台。
b。）polyphaseFilterBank_dpi_tb.do-这是指导GraphicsModelim®用于编译HDL代码并运行测试工作台模拟的宏文件。
基于所选的模拟器，编码器生成了一个不同的文件进行编译和测试基准模拟。例如，如果选择“敏锐的”，则编码器会在Cadence®Incisive®上生成“ polyphaseFilterBank_dpi_tb.sh”进行编译和仿真。
(Optional) Generate HDL Code Coverage Report and Database
启动HDL模拟器以生成HDL代码覆盖范围报告和数据库：
a。）在“ HDL代码生成>测试台式”窗格上，选择标有“ HDL代码覆盖”的复选框。
b。）当您调用“ makehdltb”时，将“ hdlcodecoverage”设置为“ on”。例如：
makehdltb('hdlcoder_dpic_testbench/polyphaseFilterBank'，，，，“ TargetDirectory”，WorkingDir，“生成vdpitestbench'，，，，HDLSimulator,'generateHdlTestBench'，，，，'离开'，，，，“ hdlcodecoverage'，，，，'上'）；
模拟测试工作台后，在源目录中生成HDL代码覆盖量。
HDL测试工作台和SystemVerilog DPI测试台的生成时间比较
The simulation time of the model is set in the pre-load callback (Model Properties > Callbacks > PreLoadFcn)
SIMTIME = 1000;
The sampling frequency is 2e+6 Hz, which means that the simulation to generate the HDL testbench collects 2e+9 samples.
For certain applications, it takes more samples to obtain the right frequency from the polyphase filter. An increase in required simTime would also increase the time required to generate an HDL test bench.
A solution for such applications is to use the SystemVerilog DPI test bench. The generation time for the test bench remains the same no matter how many samples your test scenario requires.
您可以通过更改“ SIMTIME”变量来增加仿真时间。例如，为2E+12个样本生成HDL测试台，设置：
simTime = 1000000;
The table shows a comparison of time taken (in seconds) for generation of HDL test bench and SystemVerilog DPI test bench for increasing numbers of samples (from 2e+9 to 2e+15) :
columns = {“数字样本”;“ gationTimeHdltestBench”;'GenerationTimeSystemVerilogDPITestbench'}; numSamples = [2e9;2e10;2e11;2e12;2e13;2e14;2e15]; HDLTBtime= [10;12;59;504;4994;52200;505506]; DPICTBtime=[47;47;47;47;47;47;47]; CompareTestBenchTimes = table(numSamples,HDLTBtime,DPICTBtime,'variablenames'，，，，columns); disp(CompareTestBenchTimes);
NumberOfSamples GenerationTimeHDLTestBench GenerationTimeSystemVerilogDPITestbench _______________ __________________________ _______________________________________ 2e+09 10 47 2e+10 12 47 2e+11 59 47 2e+12 504 47 2e+13 4994 47 2e+14 52200 47 2e+15 5.0551e+05 47
这两种测试台类型相对于样品数量的生成时间的日志图表明，虽然HDL测试台需要更多的生成时间，而样品数量增加，但SystemVerilog DPI测试台的生成时间仍保持不变。样品数量。
loglog(numSamples,HDLTBtime,'b-o'，numsamples，dpictbtime，'r-o'）；Xlim（[2E09 2E15]）;传奇（“ HDL测试台”，，，，“ SystemVerilog DPI测试台”，，，，'Location'，，，，'西北'）；Xlabel（“样品数量”）；ylabel（“发电时间（以秒为单位）”）；CLOSS_SYSTEM（ModelName，0）;
Conclusion
虽然HDL测试工作台对于少数样品非常有效，但如果您的测试场景需要大量样品，则HDL验证者SystemVerilog DPI测试台可提供更快的测试工作台生成。
You can also select a web site from the following list:
Americas
- América Latina(Español)
- Canada(English)
- United States(English)