Get Started withHDL Verifier

HDL Verifier™ lets you test and verify Verilog^®and VHDL^®designs for FPGAs, ASICs, and SoCs. You can verify RTL against test benches running in MATLAB^®or Simulink^®using cosimulation with an HDL simulator. These same test benches can be used with FPGA and SoC development boards to verify HDL implementations in hardware.

HDL Verifier provides tools for debugging and testing FPGA implementations on Xilinx^®and Intel^®boards. You can use MATLAB to write to and read from memory-mapped registers for testing designs on hardware. You can insert probes into designs and set trigger conditions to upload internal signals into MATLAB for visualization and analysis.

HDL Verifier generates verification models for use in RTL test benches, including Universal Verification Methodology (UVM) test benches. These models run natively in simulators that support the SystemVerilog Direct Programming Interface (DPI).

Tutorials

HDL Cosimulation

• Verify HDL Module with MATLAB Test Bench
  Set up and run a ModelSim^®and MATLAB test bench session.
• Verify HDL Module with Simulink Test Bench
  The steps for setting up an HDL Verifier session that uses Simulink to verify a simple VHDL model.

HDL Code Import

• Cosimulation Wizard for MATLAB System Object
  Set up an HDL Verifier™ application using the Cosimulation Wizard.
• Verify Raised Cosine Filter Design Using Simulink
  Provides instruction in using the Cosimulation Wizard to create a Simulink model for cosimulation.

TLM Component Generation

• Get Started with TLM Generator
  This example shows how to configure a Simulink® model to generate a SystemC™/TLM component using the tlmgenerator target for either Simulink Coder™ or Embedded Coder®.

FPGA-in-the-Loop (FIL)

• Verify HDL Implementation of PID Controller Using FPGA-in-the-Loop
  This example shows you how to set up an FPGA-in-the-Loop (FIL) application using HDL Verifier™.
• Verify Digital Up-Converter Using FPGA-in-the-Loop
  This example shows you how to verify a digital up-converter design generated with Filter Design HDL Coder™ using FPGA-in-the-Loop simulation.

验证生成的HDL Code with HDL Workflow Advisor (requiresHDL Coderlicense)

• Choose a Test Bench for Generated HDL Code(HDL Coder)
  Select a generated test bench.
• Generate Test Bench and Enable Code Coverage Using the HDL Workflow Advisor(HDL Coder)
  Generate test bench and code coverage for generated HDL code using the HDL Workflow Advisor.

Design Verification Automation

• HDL Cosimulation
  

  The HDL Verifier software consists of MATLAB functions, a MATLAB System object™, and a library of Simulink blocks, all of which establish communication links between the HDL simulator and MATLAB or Simulink.

• FPGA Verification
  

  HDL Verifier works with Simulink or MATLAB and HDL Coder™ and the supported FPGA development environment to prepare your automatically generated HDL code for implementation in an FPGA.

• TLM Component Generation
  

  HDL Verifier lets you create a SystemC Transaction Level Model (TLM) that can be executed in any OSCI-compatible TLM 2.0 environment, including a commercial virtual platform.

• SystemVerilog DPI Component Generation
  

  HDL Verifier works withSimulink Coder™orMATLAB Coderto export a subsystem as generated C code inside a SystemVerilog component with a Direct Programming Interface (DPI).

Featured Examples

Verify HDL Implementation of PID Controller Using FPGA-in-the-Loop

Set up an FPGA-in-the-Loop (FIL) application using HDL Verifier™. The application uses Simulink® and an FPGA development board to verify the HDL implementation of a proportional-integral-derivative (PID) controller. In this example, Simulink generates the desired position of a motor and simulates the motor controlled by this PID controller.

Open Example

Cosimulation Wizard for MATLAB System Object

Set up an HDL Verifier™ application using the Cosimulation Wizard.

Open Example

Tutorial: Cosimulation Wizard for MATLAB Callback Function

This tutorial guides you through the basic steps for setting up an HDL Verifier™ application using Cosimulation Wizard.

Get Started with Simulink HDL Cosimulation

Guides you through the basic steps for setting up an HDL Verifier™ application using the Cosimulation Wizard in the Simulink® environment.

Open Script

Comparing HDL and Simulink Code Coverage Using Cosimulation

Achieve complete code coverage of an HDL cruise controller design using Simulink® and an HDL Simulator.

Open Model

Get Started with SystemVerilog DPI Component Generation

Generate a SystemVerilog DPI component from a proportional-integral-derivative (PID) controller in a Simulink® model and how to export the component to an HDL simulator.

Open Model

Get Started with MATLAB Based SystemVerilog DPI Generation

Generate a SystemVerilog DPI component for a programmable square-wave generator written in MATLAB®, and export it to an HDL simulator.

Open Script

Get Started with TLM Generator

配置一个仿真软件®模型生金宝app成SystemC™/TLM component using the tlmgenerator target for either Simulink Coder™ or Embedded Coder®.

Open Script