主要内容

Transaction Level Model Generation

Generation of SystemC TLM virtual prototypes

HDL Verifier™ integrates with金宝app®Coder™or Embedded Coder®导出Systemc™TLM兼容交易级模型。您可以将此组件作为行为模型集成到HDL模拟中。

The TLM generation tool provides a default socket and memory configuration. To customize the socket and memory map of the TLM component, provide an IP-XACT™ file. You can configure the generated component to use a SystemC thread or a callback function.

HDL Verifier generates a TLM test bench, test vectors, and a makefile to verify the component and assist with integration into your HDL simulator environment.

Topics

生成TLM组件和测试台

Define Memory Map

  • Prepare IP-XACT File for Import
    要自定义要生成的组件的TLM接口，您可以将自己的IP-XACT XML文件导入到TLM Generator中。
  • 生成的IP-XACT文件的内容
    The TLM generator automatically generates an IP-XACT file that complies with IEEE®IP-XACT的标准1685-2009。
  • Implement Memory Map with SCML
    The SystemC Modeling Library (SCML) is a TLM 2.0 compatible API library for creating TLM model interfaces for use with Synopsys®prototyping tools.

导出TLM组件

  • 导出TLM组件
    代码生成完成后，请转到您的工作文件夹。
  • TLM组件的构造函数
    描述生成的TLM组件构造函数和默认参数，并提供用于更改这些参数的信息。
  • Testing TLM Components
    The test bench generation option is controlled by theTLM测试板“配置参数”对话框的选项卡。