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MATLAB AXI Master

Access AXI slave memory on FPGA board from MATLAB®

Access on-board memory locations from MATLAB, using the MATLAB AXI master IP in your FPGA design, and theaximasterobject. The object connects to the IP over a JTAG, Ethernet, or a PCIe interface and allows read and write commands to slave memory locations from the MATLAB command line.

Functions

setupAXIMasterForQuartus Add AXI master IP path toQuartusproject
readmemory Read data out of AXI4 memory-mapped slaves
writememory 将数据写入AXI4内存映射的奴隶
释放 Release JTAG or Ethernet cable resource

Objects

aximaster Read and write memory locations on FPGA board fromMATLAB

Blocks

AXI Master Read Read memory locations on FPGA board from金宝app
AXI Master Write Write memory locations on FPGA board from金宝app

Topics

Set Up MATLAB as AXI Master

High-level steps for accessing memory-mapped locations on an FPGA board from MATLAB or Simulink®.

Ethernet MATLAB as AXI Master

Integrate and configure Ethernet MATLAB as AXI Master.

PCI Express MATLAB as AXI Master

Integrate and configure MATLAB as AXI Master IP over PCI Express.

Use Simulink to Access FPGA Locations

Access memory-mapped locations on an FPGA board from Simulink.

Featured Examples

Access FPGA External Memory Using MATLAB as AXI Master

Access FPGA External Memory Using MATLAB as AXI Master

使用MATLAB作为Axi Master，访问连接到FPGA的外部DDR记忆。FPGA设计实例化了Intel DDR存储器控制器，以访问DDR记忆。该内存控制器提供了一个内存映射的从接口，用于从FPGA读取和写入操作。MATLAB作为AXI Master功能提供了AXI Master IP，该IP允许MATLAB访问FPGA中的任何内存映射从属IP。在此示例中，我们演示了如何将JTAG MATLAB作为AXI Master IP或以太网MATLAB作为AXI Master IP作为QSYS设计，然后从MATLAB读取并编写DDR存储器。
IP Core Generation Workflow Without an Embedded ARM Processor: Arrow DECA MAX 10 FPGA Evaluation Kit

IP Core Generation Workflow Without an Embedded ARM Processor: Arrow DECA MAX 10 FPGA Evaluation Kit

Use the HDL Coder™ IP Core Generation Workflow to develop reference designs for Intel® parts without an embedded ARM® processor present, but which still utilize the HDL Coder™ generated AXI interface to control the DUT. This example uses MATLAB as AXI Master IP from HDL Verifier™ to access the HDL Coder™ generated DUT registers by enabling the reference design parameter optionInsert JTAG MATLAB as AXI Master. You can then access DUT registers from MATLAB directly. Alternatively, you can use Intel Qsys (TM) JTAG to Avalon Master Bridge IP to access the FPGA registers using Tcl commands in the Qsys System Console. For Intel JTAG AXI Master, you need to create a custom reference design. The FPGA design is implemented on the Arrow DECA MAX 10 FPGA evaluation kit.
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IP Core Generation Workflow With Ethernet Based MATLAB as AXI Master: Arrow DECA MAX 10 FPGA Evaluation Kit

IP Core Generation Workflow With Ethernet Based MATLAB as AXI Master: Arrow DECA MAX 10 FPGA Evaluation Kit

Uses Ethernet based MATLAB as AXI Master IP from HDL Verifier™ to access the HDL Coder™ generated registers. MATLAB as AXI Master provides access to FPGA registers from MATLAB directly. The FPGA design is implemented on the Arrow DECA MAX 10 FPGA evaluation kit.

HDL Verifier Support Package for Intel FPGA Boards Documentation

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