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FPGA Data Capture Component Generator

Configure and generate FPGA data capture components

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Description

TheFPGA Data Capture Component Generatortool configures and generates components for capturing data from a design running on an FPGA. The generated components capture a window of signal data from the FPGA and return the data to MATLAB®or Simulink®.

FPGA Data Capture Component Generator tool

To use this tool, you must have an existing HDL design and FPGA project. To capture the signals, HDL Verifier™ generates an IP core that you must integrate into your HDL project, and deploy to the FPGA along with the rest of your design.

TheGeneratebutton in this tool generates these components:

  • HDL IP core, for integration into your FPGA design. Connect the signals you want to capture and use as triggers, and connect a clock and clock enable.

  • Generation report, with list of generated files and instructions for next steps.

  • Tool to set capture parameters and capture data to the MATLAB workspace. SeeFPGA Data Capture.

  • Customized version of thehdlverifier.FPGADataReaderSystem object™ that provides an alternative, programmatic, way to configure and capture data.

  • Simulink model that contains a customizedFPGA Data Readerblock. If you have a DSP System Toolbox™ license, this model streams the captured signals into theLogic Analyzerwaveform viewer. Otherwise, theScopeblock displays the signals.

For a workflow overview, seeData Capture Workflow.

Open the FPGA Data Capture Component Generator

At the MATLAB command prompt, enter:

generateFPGADataCaptureIP

重新加载最新的参数设计, use therestoreargument:

generateFPGADataCaptureIP('restore',true);

Examples

Parameters

Ports

The name does not have to match the signal name in your HDL files. This name is used for:

  • Input port on the generated HDL IP core. Internal to the IP, this signal is routed to the capture buffer, or to use as part of trigger condition and capture condition, depending on your selection forUse As.

  • Structure field in the captured data returned to the MATLAB workspace

  • Port on the generated Simulink block

  • Table of signals in the trigger, capture condition, and data types parameters editor at capture time

Data Types:char|string

This number is used to generate the HDL IP port definition, and contributes to the total width of the capture buffer. You can specify the data type for the captured data at capture time.

Note

If you do not have Fixed-Point Designer™, data capture can only return built-in data types, such asuint8. You must specify ports for the generated IP that match the sizes of the built-in data types, that is 1, 8, 16, 32, or 64 bits. We recommend Fixed-Point Designer to enable fixed-point data types and captured signals of any size.

When you specify a signal asData, the signal is captured to the sample buffer and returned to MATLAB, but it cannot contribute to a trigger condition and capture condition. When you specify a signal asTrigger, it is available for defining a trigger condition and capture condition at capture time, but is not captured and returned to MATLAB. You can also specify that the signal is used asBoth trigger and data.

Target

This name is used for the generated HDL IP core, the System object, and the Simulink model.

The available vendors depend on which HDL Verifier support package you have installed. There are separate support packages for Intel®(Altera®) and Xilinx®boards.

Select the language used for the generated HDL IP core asVerilogorVHDL.

Select the type of connection channel asJTAGorEthernet.

Note

Ethernet connection is available for Xilinx FPGA boards only.

Location to save the generated files, specified as the name of a folder on the host computer.

Data Types:char|string

Capture

Use this parameter to specify the size of the memory in the generated HDL IP core. The width of the memory is the total bit width of the data signals.

When you specify the sample depth, consider the number of windows you plan to configure when reading the data, because together they impact the window depth of each capture window. Thewindow depthis the sample depth divided by the number of capture windows. Specify the number of capture windows by using theNumber of capture windowsparameter in theFPGA Data Capturetool or by using the property for anhdlverifier.FPGADataReaderSystem object.

For example, if the sample depth is 4096 and the number of capture windows is 4, then each capture window has a window depth of 1024.

Use this parameter to enable a sequential trigger. To capture specified data from an FPGA, give a set of trigger conditions in multiple stages. For more information on sequential trigger, seeSequential Trigger.

When you specify theMax trigger stages, consider the maximum number of trigger stages in which you plan to configure the trigger conditions. Specify the number of trigger stages by using theNumber of trigger stagesparameter in theFPGA Data Capturetool or by using theNumTriggerStagesproperty for anhdlverifier.FPGADataReaderSystem object.

For example, if the maximum number of trigger stages is 4, then the number of trigger stages can be 1, 2, 3, or 4.

Select this parameter to include capture condition logic in the HDL IP core. Include capture condition logic to use a capture condition to control which data to capture from the FPGA. The HDL IP core evaluates the capture condition at each clock cycle and captures only the data that satisfies the capture condition. For more information on capture conditions, seeCapture Conditions.

Set up a capture condition in theFPGA Data Capturetool or thehdlverifier.FPGADataReaderSystem object.

Version History

Introduced in R2017a

See Also

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