Custom Board and Reference Design

Define and register custom reference design or custom board for Xilinx^®Zynq^®平台

HDL Coder™ can generate an IP core that you can deploy to the Xilinx Zynq Platform. You can integrate the generated IP core into the default system reference design or into your own custom reference design that you can register for the board.

Classes

`hdlcoder.Board`	Board registration object that describes SoC custom board
`hdlcoder.ReferenceDesign`	Reference design registration object that describes SoC reference design

Topics

Board and Reference Design Registration System
System for defining and registering boards and reference designs.
Register a Custom Board
Define the interface and attributes of a custom SoC board. After defining the board, you can target it using the IP Core Generation Workflow in the HDL Workflow Advisor.
Register a Custom Reference Design
Define the interface and attributes of a custom SoC reference design. After defining and registering the reference design, you can target it using the IP Core Generation Workflow in the HDL Workflow Advisor.
Define Custom Parameters and Callback Functions for Custom Reference Design
Learn how to define custom parameters and custom callback functions for your custom reference design.
Define and Add IP Repository to Custom Reference Design
Learn how you can create an IP repository and add the IP modules in the repository to your custom reference design.

Featured Examples

Define Custom Board and Reference Design for Zynq Workflow

Define and register a custom board and reference design in the Zynq® workflow.

Open Script

Authoring a Reference Design for Audio System on a Zynq Board

Build a reference design to run an audio algorithm and access audio input and output on a Zynq® board.

Authoring a Reference Design for Audio System on a ZYBO Board

Build a reference design to run an audio algorithm and access audio input and output on ZYBO™ Z7-10 board.

Running an Audio Filter on Live Audio Input Using a Zynq Board

Model an audio system and implement it on a Zynq® board using an audio reference design.

Use JTAG AXI Manager to Control HDL Coder Generated IP Core

Specify automatic insertion of the HDL Verifier™ AXI Manager IP into a reference design. This example also explains how to use MATLAB® or Simulink® to configure the HDL Coder™ generated FPGA IP core.

Field-Oriented Control of a Permanent Magnet Synchronous Machine

Model a controller and implement it on a Xilinx® Zynq™-7000 All Programmable SoC target. This example uses a ZedBoard™ with an Analog Devices® motor control FMC board. If you do not have the required hardware, you can use this example to help you develop a controller for your own hardware configuration.

Open Live Script