Introduction

This example follows the algorithm development workflow that is detailed in theDeveloping Vision Algorithms for Zynq-Based Hardware例子。如果您尚未这样做，请仔细研究该示例，以更好地了解所需的工作流程。

This algorithm corresponds to the Vision HDL Toolbox example,Harris Corner Detection。With the Support Package for Zynq-Based Vision Hardware, you get a hardware reference design that allows for easy integration of your targeted algorithm in the context of a vision system.

设置

如果您尚未这样做，请穿过Zynq支持软件包安装的指导设置向导部分。金宝app安装此支持包时，您可能已经完成了此步骤。金宝app

On the MATLABHometab, in theEnvironment部分Toolstrip，，，，clickAdd-Ons > Manage Add-Ons。定位Xilinx Zynq硬件的Visio金宝appn HDL工具箱支持包，然后单击设置。

The guided setup wizard performs a number of initial setup steps, and confirms that the target can boot and that the host and target can communicate.

For more information, seeStep 1. Setup Checklist。

Pixel-Stream Model

该模型提供了用于靶向HDL的算法的像素流实现。HDL准备就绪算法没有处理完整图像，而是在像素流界面上工作。该模型使用Image Resizeblock that allows the source video frame to be resized for better simulation performance. Alternatively, you may want to perform a crop of the video frame. The blocks in the shaded areas convert to and from pixel stream signals in preparation for targeting.

Video Source此示例的源视频来自From Multimedia File块，从多媒体文件读取视频数据，或视频截取block, that captures live video frames from an HDMI source connected to the Zynq-based hardware. To configure the source, right-click on the variant selection icon in the lower-left corner of the图像源block, chooseLabel mode active choice，，，，and select eitherFileorHW。

对于此算法，该模型的配置如列出：

算法配置The algorithm, in addition to processing the image for corner detection has some control as well.

定位后，cSliceLevel，，，，cOverlayColorandcoverlaytranspparameters are controllable from the Simulink model throughExternal ModeorTarget Hardware执行。pbCornerOnly控制端口是目标设计中的纯硬件连接。该端口可以以任何理想的速率运行，包括以像素时钟速率。

However,cSliceLevel，，，，coverlaytranspandcOverlayColor值由嵌入式处理器控制（或主机External ModeorTarget Hardwaremode). Because neither the host nor the embedded CPU can update these controls at the pixel clock rate, a rate on the order of the frame rate is desired. The sample times of the constant blocks attached to these controls are set to execute at theframeSampleTime。

There are two things to note about the simulation outputs:

You can optionally run this simulation without hardware. To modify the frame size for simulation performance, change theFrame size价值Image Resize，，，，图像框架到像素，，，，andImage Pixels To Frameblocks. The lower the frame size, the faster the simulation will run. The minimum frame size is 240p.

靶向算法

对像素流算法模拟感到满意后，您可以将像素算法定位到Zynq板上的FPGA。

In preparation for targeting, set up the Xilinx tool chain by invokinghdlsetuptoolpath。For example:

>> hdlsetuptooppath（'ToolName'，，，，'Xilinx Vivado'，，，，'ToolPath'，，，，'c：\ xilinx \ vivado \ 2020.2 \ bin \ vivado.bat');

Executehdlsetuptoolpath(HDL Coder)for more information.

Start the targeting workflow by right clicking the角覆盖算法subsystem and selectingHDL代码> HDL工作流顾问。

Execute each step in sequence to experience the full workflow, or, if you are already familiar with preparation and HDL code generation phases, right-click Step 4.1 in the table of contents on the left hand side and selectRun to selected task。

Steps 4.3 and 4.4

The rest of the workflow generates a bitstream for the FPGA, downloads it to the target, and reboots the board.

Because this process can take 20-40 minutes, you can choose to bypass this step by using a pre-generated bitstream for this example that ships with product and was placed on the SDCard during setup.

笔记：该比特流是用HDMI像素时钟约束至148.5 MHz生成的，每秒60帧时最大分辨率为1080p HDTV。要在Zynq硬件上以更高的分辨率运行此示例，请从步骤1.2中的下拉列表中选择源视频分辨率值。

To use this pre-generated bitstream execute the following:

>> vz = visionzynq（）;>> changefpgaimage（vz，'Visionzynq-Zedboard-HDMicam-Corner_overlay.bit');

要使用另一个平台的Bitstream，请用平台名称替换“ Zedboard”。

Alternatively, you can continue with Steps 4.3 and 4.4.

Using the Generated Models from the HDL Workflow Advisor

步骤4.2根据是否安装了嵌入式编码器，生成了两个或四个模型：“目标硬件接口”模型和关联的库模型以及“软件接口”模型和关联的库模型。“目标硬件接口”模型可用于控制Simulink模型的参考设计，而无需嵌入编码器。金宝app安装了嵌入式编码器和Zynq（嵌入式编码器）支持软件包时，“软金宝app件接口”模型支持针对Zynq的完整软件，并启用外部模式仿真，在循环中的处理器和完整部署。

The library models are created so that any changes to the hardware generation model are propagated to any custom targeted hardware simulation or software interface models that exist.

目标硬件接口模型：In this model, you can adjust the configuration of the reference design and read or drive control ports of the hardware user logic. These configuration changes affect the design while it is running on the target. You can also display captured video from the target device.

Software Interface Model:In this model, you can run in External mode to control the configuration of the reference design, and read or drive any control ports of the hardware user logic that you connected to AXI-Lite registers. These configuration changes affect the design while it is running on the target. You can use this model to fully deploy a software design. (This model is generated only if Embedded Coder and the Embedded Coder Zynq support package are installed.)