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PLL Design and Verification Using Data Sheet Specifications

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This example shows how to use Mixed-Signal Blockset™ to model a commercial off-the-shelf integer-N phase-locked loop (PLL) with dual modulus prescaler operating around 4 GHz. You can verify the PLL performance, including phase noise.

您可以使用PLL模型来探索和设计不同的循环过滤器，模拟不同的工作频率，确定不同的分隔比，或评估嵌入较大系统中的频率合成器性能。例如，如果您需要将PLL集成到芯片或系统上的系统中，则混合信号模块PLL模型可能会有所帮助。

对于此示例，请使用Skyworks Sky73134-11. This is a wideband PLL Frequency Synthesizer operating between 350 MHz and 6.2 GHz.

Build VCO Model

打开模型vco_model, which has VCO and VCO Testbench blocks from Mixed-Signal Blockset connected together.

模型='VCO_model'; open_system(model);

Inspect the data sheet to identify the characteristics of the voltage controlled oscillator (VCO). VCO is the main component contributing to the phase noise of the PLL. Table 6 of the data sheet lists the typical VCO sensitivity (Kvco）为20 MHz/v。设置Voltage Sensitivityvco块20E6Hz/v。数据表不提供免费的运行频率（Fo) of the VCO, so you can set it to an arbitrary value close to the operting frequency. In this case, setFree running frequencyto3.9e9赫兹。

For this example, simulate the PLL behavior when the PLL locks around 4 GHz. Table 7 of the data sheet lists the VCO phase noise profile as: around 4 GHz is,

  • −105 dBc/Hz at 100 kHz

  • −131 dBc/Hz at 1 MHz

  • −142 dBc/Hz at 3 MHz

  • −152 dBc/Hz at 10 MHz

使用相位噪声曲线将相位噪声障碍添加到VCO中。为了加快模拟的速度，请忽略较低频率偏移处的相位噪声数据点。仿真需要更长的时间来捕获靠近载体的相位噪声曲线。

测量VCO相位噪声

The testbench provides the control voltage (vctrl) stimulus to the VCO and measures the VCO phase noise. The output frequency (F) of the VCO is :

$$F = Kvco * Vctrl + Fo$$

Substituting the values for the output frequency, the free running frequency, and the voltage sensitivity, the equation gives a control voltage of be 5 V.

Click on自动填充设置参数和Autofill target metric按钮可以自动填充设置和目标度量的测量参数。目标度量提供了预期的相位噪声曲线，以与模拟结果进行比较。TestBench设置属性定义了信号采样频率和测量分辨率带宽。

To speed up simulation time, reduceNo. of spectral averagesto4.

Run the simulation. Verify that the VCO model reproduces the phase noise profile specified in the target metric.

现在，您可以继续对完整的PLL系统进行建模并验证其相位噪声性能。

Build PLL Model

From theFeaturessection of the data sheet, see that this PLL is of type integer-N and it uses a dual modulus prescaler. The data sheet also provides the settings for the prescaler. Hence, use the带有双模量预定器的整数N PLL从混合信号区块中。

bdclose（模型）;模型='PLL_model'; open_system(model);

打开PLL块的面具，并为每个子系统提供规格：

  • 相频率检测器— For the phase frequency detector (PFD), the data sheet does not provide any detail. Leave the deadband compensation to its default value.

  • Charge Pump- 对于电荷泵，数据表提供了2.7 MA电流的典型值（数据表，表5）。在PLL模型中指定相同的值。

  • VCO— For the VCO, use the same specifications used in theBuild VCO Modelsection. The sensitivity is equal to20MHz/v。指定一个接近最终锁定频率的免费运行频率，例如4.18GHz。将相位噪声与刚刚模拟相同的噪声轮廓包含。

  • 分隔线— For the PLL to lock at 4.2 GHz when using a reference oscillator operating at 1.6 MHz (data sheet, Figure 17), the divider ratio is equal to:

$$\frac{4\ldotp 2\textrm{e9}}{1\ldotp 6\textrm{e6}}=2625$$

来哦ieve the effective divider ratio of 2625, set the预拉分隔线值to16,Swallow counter valueto17， 和程序计数器值to163.

  • Loop Filter— The data sheet provides the recommended loop filter component values in Figure 22. Manually input these values to implement the filter. Set Loop filter type to 3rd order passive. Also set the loop filter component values:

C1 =100E-12F

C2 =2.2e-9F

C3 =100E-12F

R2 =10e3$$\Omega $$

R3 =2.2e3$$\Omega $$

Verify the closed and open loop performance of the PLL with this implementation of the loop filter. The resulting phase margin is 55 degrees. The phase margin along with the pole zero locations confirm the stability of the PLL.

使用此设置来设计不同的循环过滤器并验证您的设计。例如，在不同的工作频率上使用此PLL。

最后，要验证时域中的PLL锁定行为，请探测和绘制环路过滤器的输出信号。

测量PLL性能

将PLL连接到混合信号模块盘PLL测试台以验证其性能。测试板定义用于测试PLL的刺激。在这种情况下，使用具有1.6 MHz频率的方波形。

设置测试台以测量工作频率，锁定时间和相位噪声。数据表指定1 ms锁定时间，其中1 ppm频率误差，即4.2 kHz（表5）。提供相同的误差容量。为了测量相位噪声，请使用类似于用于VCO的配置，但要降低分辨率带宽以提高精度。

For the target metric, refer to the data sheet for both the lock time (Table 5) and the closed loop phase noise measurements performed on the evaluation board (Figure 17). The phase noise profile measured at 4.2 GHz is:

  • -98 DBC/Hz 100 kHz

  • -129 DBC/Hz在1 MHz时

  • -150 DBC/Hz 10 MHz

使用此设置，运行PLL模拟并验证性能。

In this case, the simulation takes a few minutes. To speed up simulation time, you can relax the settings for measuring the phase noise. For example, use a larger resolution bandwidth or reduce the number of spectral averages.

模拟结果与数据表中报告的相位噪声测量值非常吻合。

参考

Skyworks Sky73134-11

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