HDL Verifier™ Support Package for Xilinx^®FPGA Boardscontains the board definition files for FPGA-in-the-loop (FIL) simulation with HDL Verifier and supported Xilinx FPGA and Zynq^®SoC boards. With FIL simulation, use MATLAB^®or Simulink^®to test designs in real hardware for any existing HDL code. FPGA data capture support lets you observe signals from your design in MATLAB while the design is running on the Xilinx FPGA or Zynq SoC. With MATLAB AXI Master IP, you can read from or write to on-board memory locations using MATLAB.