样品控制总线选择器

Select signals from the control signal bus used withWireless HDL Toolboxblocks

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库:
Wireless HDL Toolbox / Utilities

Description

The样品控制总线选择器block selects signals from thesamplecontrolbus. This bus is used for modeling streaming control signals in communication systems for hardware. SeeSample Control Bus.

The block is an implementation of the Simulink^®Bus Selectorblock. SeeBus Selectorfor more information.

Ports

Input

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`ctrl`— Control signals accompanying sample stream
`samplecontrol`bus

Control signals accompanying the sample stream, specified as asamplecontrolbus. The bus includes thestart,end, andvalidcontrol signals, which indicate the boundaries of the frame and the validity of the samples.

start— Indicates the start of the input frame
end— Indicates the end of the input frame
valid— Indicates that the data on the inputdataport is valid

For more details, seeSample Control Bus.

Data Types:bus

Output

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`start`— Start of frame
scalar

Start of frame, returned as aBooleanscalar. This signal is 1 (true) for one time step, corresponding to the first valid sample of the frame.

Data Types:Boolean

`end`— End of frame
scalar

End of frame, returned as aBooleanscalar. This signal is 1 (true) for one time step, corresponding to the last valid sample of the frame.

Data Types:Boolean

`valid`— Validity of samples
scalar

Validity of samples, returned as aBooleanscalar. This signal is 1 (true) on time steps that correspond to valid samples.

Data Types:Boolean

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

To learn more about using buses for HDL code generation, seeBuses(HDL Coder)andUse Bus Signals to Improve Readability of Model and Generate HDL Code(HDL Coder).

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is`0`. For more details, seeConstrainedOutputPipeline(HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is`0`. For more details, seeInputPipeline(HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is`0`. For more details, seeOutputPipeline(HDL Coder).

Version History

Introduced in R2017b

样品控制总线选择器

Description

Ports

Input

`ctrl`— Control signals accompanying sample stream
`samplecontrol`bus

Output

`start`— Start of frame
scalar

`end`— End of frame
scalar

`valid`— Validity of samples
scalar

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Version History

See Also

Blocks

Functions

Topics

样品控制总线选择器

Description

Ports

Input

ctrl— Control signals accompanying sample streamsamplecontrolbus

Output

start— Start of framescalar

end— End of framescalar

valid— Validity of samplesscalar

Extended Capabilities

C/C++ Code GenerationGenerate C and C++ code using Simulink® Coder™.

HDL Code GenerationGenerate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Version History

See Also

Blocks

Functions

Topics

`ctrl`— Control signals accompanying sample stream
`samplecontrol`bus

`start`— Start of frame
scalar

`end`— End of frame
scalar

`valid`— Validity of samples
scalar

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.