Introduction

The model shows how to use HDL Optimized CRC Generator and Detector library blocks for simulation and HDL Code generation. The 802.11 standard is used as the application. To learn more about HDL support for HDL Optimized CRC blocks, refer to thedocumentation. To learn more about the algorithm used in the blocks, refer to the paper in [2].

To open this example model, run the following commands:

modelname ='commcrchdl'; open_system(modelname);

In this model, the top-level subsystemCRC Subsystemcontains the HDL Optimized CRC Generator and Detector blocks. This subsystem also has anAddNoisesubsystem that you can choose to add noise to the generated CRC checksum. To open this subsystem, run the following commands:

systemname = [modelname'/CRC Subsystem']; open_system(systemname);

Parameter Settings

CRC-CCITT is used in the IEEE® 802.11 standard to protect the SIGNAL, SERVICE and LENGTH fields. The row vector [1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1] represent the polynomial:

The HDL optimized CRC Generator block in the demo uses the Direct Method, i.e. it feeds the message into the most significant bit (MSB) of the checksum shift register and processes the message without padding zeros. The details of the CRC implementation can be found inthis model. The diagram of the IEEE 802.11 CRC implementation is illustrated in Figure 15-2 of the 802.11 standard. The initial state is set as 1.

The final XOR value is set as0xFFFFto implement the ones complement of the CRC Checksum.

Input Signals

The test vector in this model uses the example DBPSK signal specified in the 802.11 standard. The test data padded with CRC_length zeros is processed at 16 bits/sample in streaming mode. ParameterdataIn_width, which is the port width of the CRC Generator input port dataIn, defines the data processing speed.mlendefines the period in the controls signals startIn, endIn, and validIn.dlendefines the pulse width of the validIn signal. The input signals are configured in theInitFcncallback function in theModel Propertiesdialog box.

%DBPSK datadata = [0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0]; crc_len = 16;% pad crc_len zeromsg = [data zeros(1,crc_len)]; dataIn_width = 16; mlen = length(msg)/dataIn_width; dlen = length(data)/dataIn_width;

You can alter the dataIn_width to 8,4,2,1 bit(s) in this example to meet your design requirements.For example, if you are processing data with length 56, aside from padding 8 bit zeros and usingdataIn_with16, you can choosedataIn_widthto be 8 to ensure mlen and dlen are all integer numbers.

Output Signals

Run the model using the following command:

sim(modelname);

Several of the key signals have been logged into the workspace. These signals can be viewed in a Logic Analyzer window. The function commcrchdl_plot shows how to set the Logic Analyzer display. For further information on the Logic Analyzer System object™, refer to thedsp.LogicAnalyzer.

h = commcrchdl_plot(dataIn,startIn,endIn,validIn,...dataOut_gen,startOut_gen,endOut_gen,validOut_gen,...dataIn_det,dataOut_det,startOut_det,endOut_det,validOut_det,err);

dataIn,startIn,endIn, andvalidInare input data and control signals to the HDL CRC generator.dataOut_gen(output of CRC generator) displays the message with the checksum appended everydataIn_widthbits per sample. You can read the checksum whenendOut_genis high in the output waveform. The value0x5B57matches the CRC-16 FCS specified in 802.11 standard Section 15.2.3.6.dataIn_det显示消息和the corrupted checksum.dataOut_detdisplays the message output of the CRC detector. Error is detected when theerrsignal is high.erris valid when theendOut_detis active.

Initial delays are introduced at the output of the CRC generator and detector. You can calculate the initial delays using the following command:

initial_delay_gen = crc_len/dataIn_width + 2; initial_delay_det = 4*crc_len/dataIn_width + 4;

Check and Generate HDL Code

To check and generate HDL code of this example, you must have an HDL Coder™ license.

You can use the commandsmakehdl(subsystemname)andmakehdltb(subsystemname)to generate the HDL code and testbench for the subsystemsHDL CRC in TransmitterandHDL CRC in Receiver.

Specify the subsystemname as 'commcrchdl/CRC Subsystem/HDL CRC in Transmitter' or 'commcrchdl/CRC Subsystem/HDL CRC in Receiver'.

Selected References