Video Processing Acceleration Using FPGA-in-the-Loop

这个示例使用:

Open Example

This example uses FPGA-in-the-Loop (FIL) simulation to accelerate a video processing simulation with Simulink® by adding an FPGA. The process shown analyzes a simple system that sharpens an RGB video input at 24 frames per second.

This example uses the Computer Vision Toolbox™ in conjunction with HDL Coder™ and HDL Verifier™ to show a design workflow for implementing FIL simulation.

Tools required to run this example:

FPGA design software (Xilinx® ISE® or Vivado® design suite or Intel® Quartus® Prime design software)
One of the supported FPGA development boards and accessories (the ML403, SP601, BeMicro SDK, and Cyclone III Starter Kit boards are not supported for this example). For more information about supported hardware, seeSupported FPGA Devices for FPGA Verification.
For connection using Ethernet: Gigabit Ethernet Adapter installed on host computer, Gigabit Ethernet crossover cable
For connection using JTAG: USB Blaster I or II cable and driver for Altera FPGA boards. Digilent® JTAG cable and driver for Xilinx FPGA boards.
For connection using PCI Express®: FPGA board installed into PCI Express slot of host computer.

MATLAB® and FPGA design software can either be locally installed on your computer or on a network accessible device. If you use software from the network you will need a second network adapter installed in your computer to provide a private network to the FPGA development board. Consult the hardware and networking guides for your computer to learn how to install the network adapter.

1. Open and Execute the Simulink Model

Open the model and run the simulation for 0.21s.

Due to the large quantity of data to process , the simulation is not fluent. We will improve the simulation speed in the following steps by using a FPGA-in-the-Loop.

2. Generate HDL Code

Generate HDL code for the Streaming Video Sharpening subsystem by performing these steps:

a.Right-click on the block labeledStreaming 2-D FIR Filter.

b.SelectHDL Code > Generate HDL for Subsystemin the context menu.

Alternatively, you can generate HDL code by entering the following command at the MATLAB prompt:

makehdl('fil_videosharp_sim/Streaming 2-D FIR Filter')

If you do not want to generate HDL code, you can use the pre-generated HDL files located in thevideosharp_hdlsrcfolder.

3. Set Up FPGA Design Software

Before using FPGA-in-the-Loop, make sure your system environment is set up properly for accessing FPGA design software. You can use the functionhdlsetuptoolpathto add Xilinx Vivado or Intel Quartus Prime to the system path for the current MATLAB session.

For Xilinx FPGA boards, run

hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath','C:\Xilinx\Vivado\2019.2\bin');

This example assumes that the Xilinx Vivado executable is located in C:\Xilinx\Vivado\2019.2\bin. Substitute with your actual executable location if it is different.

For Intel boards, run

hdlsetuptoolpath('ToolName','Altera Quartus II','ToolPath','C:\Intel\quartus\18.1\bin64');

This example assumes that the Intel Quartus Prime executable is located in C:\Intel\quartus\18.1\bin64. Substitute with your actual executable location if it is different.

4. Run FPGA-in-the-Loop Wizard

Enter the following command at the MATLAB prompt to launch the FIL Wizard:

filWizard;

4.1 Hardware Options

Select a board in the board list.

4.2 Source Files

a.Add the previously generated HDL source files for theStreaming Video Sharpeningsubsystem.

b.SelectStreaming_2_D_FIR_Filter.vhdas the Top-level file.

4.3 DUT I/O Ports

Do not change anything in this view.

4.4 Build Options

a.Select an output folder.

b.Click Build to build the FIL block and the FPGA programming file.

During the build process, the following actions occur:

A FIL block named Streaming_2_D_FIR_Filter is generated in a new model. Do not close this model.
After new model generation, the FIL Wizard opens a command window where the FPGA design software performs synthesis, fit, place-and-route, timing analysis, and FPGA programming file generation. When the FPGA design software process is finished, a message in the command window lets you know you can close the window. Close the window.

c.Close the fil_videosharp_sim.slx model.