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生成一个IP核心forIntelSoC Platform fromMATLAB

生成一个IP核心

To generate a custom IP core to target the Altera®Cyclone V SoC development kit or Arrow SoC kit development board:

  1. Create an HDL Coder™ project containing your MATLAB®design and test bench, or open an existing project.

  2. In the HDL Workflow Advisor, define input types and perform fixed-point conversion.

    To learn how to convert your design to fixed-point, seeBasic HDL Code Generation and FPGA Synthesis from MATLAB.

  3. In the HDL Workflow Advisor, in theSelect Code Generation Targettask:

    • Workflow: SelectIP Core Generation.

    • 平台: Select your target hardware from the drop-down list.

      If you do not see your target hardware in the list, selectGet moreto download the target support package.

    • Additional source files: If you are using anhdl.BlackBoxSystem object™ to include existing Verilog®or VHDL®code, enter the file names. Enter each file name manually, separated with a semicolon (;), or by using the...button.

  4. In theSet Target Interfacestep, for each port, select an option from theTarget Platform Interfacesdrop-down list.

  5. In theHDL Code Generationstep, optionally specify code generation options, then clickRun.

  6. In the HDL Workflow Advisor message pane, click the IP core report link to view detailed documentation for your generated IP core.

To learn more about custom IP core generation, seeCustom IP Core Generation.

Requirements and Limitations

To map your DUT ports to an AXI4 interface, the input and output ports must:

  • Have a bit width less than or equal to 32 bits.

  • Be scalar.