内存

Output input from previous time step

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库:
Simulink / Discrete
HDL Coder / Discrete

Description

The内存block holds and delays its input by one major integration time step. When placed in an iterator subsystem, it holds and delays its input by one iteration. This block accepts continuous and discrete signals. The block accepts one input and generates one output. Each signal can be a scalar, vector, matrix, or N-D array. If the input is non-scalar, the block holds and delays all elements of the input by the same time step.

You specify the block output for the first time step using theInitial conditionparameter. Careful selection of this parameter can minimize unwanted output behavior. However, you cannot specify the sample time. This block’s sample time depends on the type of solver used, or you can specify to inherit it. TheInherit sample timeparameter determines whether sample time is inherited or based on the solver.

Tip

Avoid using the Memory block when both these conditions are true:

Your model uses the variable-step solverode15sorode113.
The input to the block changes during simulation.

When the Memory block inherits a discrete sample time, the block is analogous to theUnit Delayblock. However, the Memory block does not support state logging. If logging the final state is necessary, use aUnit Delayblock instead.

Comparison with Similar Blocks

The内存,Unit Delay, andZero-Order Holdblocks provide similar functionality but have different capabilities. Also, the purpose of each block is different.

This table shows recommended usage for each block.

Block	Purpose of the Block	Reference Examples
Unit Delay	Implement a delay using a discrete sample time that you specify. The block accepts and outputs signals with a discrete sample time.	Engine Timing Model with Closed Loop Control(Compression subsystem)
内存	Implement a delay by one major integration time step. Ideally, the block accepts continuous (or fixed in minor time step) signals and outputs a signal that is fixed in minor time step.	Building a Clutch Lock-Up Model(Friction Mode Logic/Lockup FSM subsystem) Capture the Velocity of a Bouncing Ball with the Memory Block
Zero-Order Hold	Convert an input signal with a continuous sample time to an output signal with a discrete sample time.	Developing the Apollo Lunar Module Digital Autopilot Radar Tracking Using MATLAB Function Block

Each block has the following capabilities.

Capability	内存	Unit Delay	Zero-Order Hold
Specification of initial condition	Yes	Yes	No, because the block output at time t = 0 must match the input value.
Specification of sample time	No, because the block can only inherit sample time from the driving block or the solver used for the entire model.	Yes	Yes
Support for frame-based signals	No	Yes	Yes
Support for state logging	No	Yes	No

Bus Support

The内存block is a bus-capable block. The input can be a virtual or nonvirtual bus signal subject to the following restrictions:

Initial conditionmust be zero, a nonzero scalar, or a finite numeric structure.
IfInitial conditionis zero or a structure, and you specify aState name, the input cannot be a virtual bus.
IfInitial conditionis a nonzero scalar, you cannot specify aState name.

For information about specifying an initial condition structure, seeSpecify Initial Conditions for Bus Elements.

All signals in a nonvirtual bus input to a内存block must have the same sample time, even if the elements of the associated bus object specify inherited sample times. You can use aRate Transitionblock to change the sample time of an individual signal, or of all signals in a bus. SeeModify Sample Times for Nonvirtual BusesandBus-Capable Blocksfor more information.

You can use an array of buses as an input signal to a内存block. You can specify theInitial conditionparameter with:

The value0. In this case, all the individual signals in the array of buses use the initial value0.
An array of structures that specifies an initial condition for each of the individual signals in the array of buses.
A single scalar structure that specifies an initial condition for each of the elements that the bus type defines. Use this technique to specify the same initial conditions for each of the buses in the array.

For details about defining and using an array of buses, seeGroup Nonvirtual Buses in Arrays of Buses.

Ports

Input

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`Port_1`— Input signal
标量|vector | matrix | N-D array

Input signal, specified as a scalar, vector, matrix, or N-D array. The input can be continuous or discrete, containing real, or complex values of any data type Simulink^®supports.

Output

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`Port_1`— Input delayed by one major integration time step
标量|vector | matrix | N-D array

Output is the input from the previous time step.

Parameters

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Main

`Initial condition`— Initial condition
0 (default) | scalar | vector | matrix | N-D array

Specify the output at the initial integration step. This value must be 0 when you do not use a built-in input data type.

Programmatic Use

Block Parameter:InitialCondition

Type:character vector

Values:标量|vector

Default:'0'

`Inherit sample time`— Inherit sample time
`off`(default) |`on`

Select to inherit the sample time from the driving block:

If the driving block has a discrete sample time, the block inherits the sample time.
If the driving block has a continuous sample time, selecting this check box has no effect. The sample time depends on the type of solver used for simulating the model.

When this check box is cleared, the block sample time depends on the type of solver used for simulating the model:

If the solver is a variable-step solver, the block sample time is continuous but fixed in minor time step:[0, 1].
如果解算器是一个固定的解算器,[0, 1]sample time converts to the solver step size after sample-time propagation.

Programmatic Use

Block Parameter:InheritSampleTime

Type:character vector

Values:'off' | 'on'

Default:'off'

`Direct feedthrough of input during linearization`— Output the input during linearization and trim
`off`(default) |`on`

Select to output the input during linearization and trim. This selection sets the block mode to direct feedthrough.

Selecting this check box can cause a change in the ordering of states in the model when using the functionslinmod,dlinmod, ortrim. To extract this new state ordering, use the following commands.

First compile the model using the following command, wheremodelis the name of the Simulink model.

[sizes, x0, x_str] = model([],[],[],'lincompile');

Next, terminate the compilation with this command.

model([],[],[],'term');

The output argument,x_str, which is a cell array of the states in the Simulink model, contains the new state ordering. When passing a vector of states as input to thelinmod,dlinmod, ortrimfunctions, the state vector must use this new state ordering.

Programmatic Use

Block Parameter:LinearizeMemory

Type:character vector

Values:'off' | 'on'

Default:'off'

`Treat as a unit delay when linearizing with discrete sample time`— Linearize to unit delay for discrete inputs
`off`(default) |`on`

Select to linearize the内存block to a unit delay when the内存block is driven by a signal with a discrete sample time.

Programmatic Use

Block Parameter:LinearizeAsDelay

Type:character vector

Values:'off' | 'on'

Default:'off'

State Attributes

`State name`— Unique name for block state
`''`(default) | alphanumeric string

Use this parameter to assign a unique name to the block state. The default is' '. When this field is blank, no name is assigned. When using this parameter, remember these considerations:

A valid identifier starts with an alphabetic or underscore character, followed by alphanumeric or underscore characters.
The state name applies only to the selected block.

This parameter enablesState name must resolve to Simulink signal objectwhen you clickApply.

For more information, seeC Code Generation Configuration for Model Interface Elements(Simulink Coder).

Programmatic Use

Block Parameter:StateName

Type:character vector

Values:unique name

Default:''

`State name must resolve to Simulink signal object`— Require state name resolve to a signal object
`off`(default) |`on`

Select this check box to require that the state name resolves to a Simulink signal object.

Dependencies

To enable this parameter, specify a value forState name. This parameter appears only if you set the model configuration parameterSignal resolutionto a value other thanNone.

Programmatic Use

Block Parameter:StateMustResolveToSignalObject

Type:character vector

Values:'off' | 'on'

Default:'off'

Model Examples

Calculate and Display Simulation Step Size using Memory and Clock Blocks

Use the Memory and Clock blocks to calculate and display the step size in a simulation.

Open Model

Capture the Velocity of a Bouncing Ball with the Memory Block

Thesldemo_bounceexample shows how to use the Second-Order Integrator and Memory blocks to capture the velocity of a bouncing ball just before it hits the ground.

Open Model

Implement a Finite-State Machine with the Combinatorial Logic and Memory Blocks

Thesldemo_clutchexample shows how you can use the Memory block with the Combinatorial Logic block to implement a finite-state machine.

Open Model

Block Characteristics

Data Types	`Boolean`\|`bus`\|`double`\|`enumerated`\|`fixed point`\|`integer`\|`single`
Direct Feedthrough	`yes`
Multidimensional Signals	`yes`
Variable-Size Signals	`no`
Zero-Crossing Detection	`no`

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is`0`. For more details, seeConstrainedOutputPipeline(HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is`0`. For more details, seeInputPipeline(HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is`0`. For more details, seeOutputPipeline(HDL Coder).
ResetType	Suppress reset logic generation. The default is`default`, which generates reset logic. See alsoResetType(HDL Coder).

Complex Data Support

This block supports code generation for complex signals.

内存