Main Content

Ethernet AXI Manager

Note

Ethernet AXI master has been renamed to Ethernet AXI manager and the UDP MATLAB®as AXI Master IP has been renamed to the UDP AXI Manager IP. In the software and documentation, the terms "manager" and "subordinate" replace "master" and "slave," respectively.

Integrate and configure AXI manager over Ethernet using user datagram protocol (UDP). To use Ethernet AXI manager, you must first include these two intellectual property (IP) blocks in your project: Ethernet media access controller (MAC) Hub and UDP AXI Manager.

Ethernet MAC Hub IP

The Ethernet MAC Hub IP connects the Ethernet physical layer (PHY) to the UDP AXI Manager IP. Use the following Ethernet MAC Hub IPs to connect the target FPGA board through various types of interfaces.

  • Ethernet MAC Hub GMII IP — This IP supports the gigabit media independent interface (GMII).

  • Ethernet MAC Hub MII IP — This IP supports the media independent interface (MII).

  • Ethernet MAC Hub GMII IP and 1G/2.5G Ethernet PCS/PMA or SGMII Xilinx®IP — Connect these two IPs to support the serial gigabit media independent interface (SGMII).

Interface of Ethernet MAC Hub IP

Interface of Ethernet MAC Hub IP

The following tables provide the port description of Ethernet MAC Hub GMII and Ethernet MAC Hub MII.

Port Description
s0_axis AXI-stream下属接口。连接这个运动t to them_axisport on the UDP AXI Manager IP.
m0_axis AXI-stream manager interface. Connect this port to thes_axisport on the UDP AXI Manager IP.

Ethernet MAC Hub GMII IP Ports

Port Direction Description
ref_clk Input Reference clock signal that drivesphy_gtxclk. The frequency ofref_clkmust be the same as thephy_rxclkclock frequency.
ref_reset Input IP reset signal.
phy_rxclk Input Receive clock from PHY.
phy_rxd[7:0] Input Receive data signal from PHY.
phy_rxdv Input Receive data valid control signal from PHY.
phy_rxer Input Receive error signal from PHY.
rxclk_en Input Receiver clock enable.
txclk_en Input 发射机时钟使.
phy_col Input Collision detect signal from PHY.
phy_crs Input Carrier sense detect signal from PHY.
axis_aclk Input Clock signal for AXI-stream interface.
phy_gtxclk Output Clock to PHY.
phy_txd[7:0] Output Transmit data signal to PHY.
phy_txen Output Transmit enable control signal to PHY.
phy_txer Output Transmit error signal to PHY.
axis_aresetn Output Active-low reset. Reset signal for AXI-stream interface. You can use this port to reset the downstream AXI peripherals.

Ethernet MAC Hub MII IP Ports

Port Direction Description
axis_aclk Input Clock signal for AXI-stream interface.
重置 Input IP reset signal.
mii_col Input Collision detect signal from PHY.
mii_crs Input Carrier sense detect signal from PHY.
mii_rxclk Input Receive clock signal from PHY.
mii_rxd[3:0] Input Receive data signal from PHY.
mii_rxdv Input Receive data valid control signal from PHY.
mii_rxer Input Receive error signal from PHY.
mii_txclk Input Transmit clock signal from PHY.
axis_aresetn Output Active-low reset. Reset signal for AXI-stream interface. You can use this port to reset the downstream AXI peripherals.
mii_txd[3:0] Output Transmit data signal to PHY.
mii_txen Output Transmit enable control signal to PHY.
mii_txer Output Transmit error signal to PHY.
phy_mdc Output Management data clock (MDC) signal to PHY.
phy_mdio Inout Data signal for communication with management data input/output (MDIO) controller.
phy_reset_n Output Active-low reset signal to PHY.

For more information about port connections, seeAccess FPGA Memory Using Ethernet-Based AXI Manager.

Ethernet MAC Hub IP Connections for SGMII

For an SGMII, connect the Ethernet MAC Hub GMII IP to the 1G/2.5G Ethernet PCS/PMA or SGMII Xilinx IP as this figure shows.

Ethernet MAC Hub IP connections for SGMII

Ethernet MAC Hub IP Parameters

Based on the type of Ethernet interface of your target FPGA board, instantiate the Ethernet MAC Hub GMII or Ethernet MAC Hub MII HDL IP in your design. After instantiating the Ethernet MAC Hub IP in your design, open the block parameters for configuration. This figure shows the block parameters for the Ethernet MAC Hub GMII IP.

Ethernet MAC Hub IP parameters

Configure these parameters:

  • Number of AXI Stream Channels— This parameter decides the number of AXI-stream channels in the Ethernet MAC Hub IP. Select this value as an integer from 1 to 8. The default value is1.

  • IP Address Byte1, IP Address Byte2, IP Address Byte3, IP Address Byte4— These parameters set the four bytes in the range from 0 to 255 composing the UDP internet protocol (IP) address of the device. This address must match theDeviceAddressproperty value of theaximanagerobject.

  • UDP Port For Channel 1, UDP Port For Channel 2, UDP Port For Channel 3, UDP Port For Channel 4, UDP Port For Channel 5, UDP Port For Channel 6, UDP Port For Channel 7, UDP Port For Channel 8— These parameters set the UDP port numbers. Specify each parameter value as an integer from 255 to 65,535. These port numbers must match thePortproperty value of theaximanagerobject.

Ethernet MAC Hub IP Limitations

  • For SGMII, the clock signal for the AXI-Stream interface (axis_aclk) is limited to 50 MHz.

  • Ethernet management interfaces MDC and MDIO do not enable you to configure the Ethernet PHY.

UDP AXI Manager IP

The UDP AXI Manager HDL IP connects the Ethernet MAC Hub IP to your application IP. The UDP AXI Manager IP acts as a bridge that translates data between an AXI peripheral and MATLAB.

Interface of UDP AXI Manager IP

Interface of UDP AXI Manager IP

The interface of the UDP AXI Manager IP includes the ports described in these tables.

Port Description
s_axis AXI-stream下属接口。
m_axis AXI-stream manager interface.
axi4m AXI4-full manager interface.

UDP AXI Manager IP Ports

Port Direction Description
axis_aclk Input Clock signal for AXI-stream interface.
axis_aresetn Input Active-low reset signal for AXI-stream interface.
aclk Input Clock signal for AXI4-full interface.
aresetn Input Active-low reset. Reset signal for AXI4-full interface.

UDP AXI Manager IP Parameters

After instantiating the UDP AXI Manager IP in your design, open the block parameters for configuration.

UDP AXI Manager IP parameters

Configure these parameters:

  • AXI Address Width— This parameter is the address bus width in bits. The IP supports 32 bits or 64 bits.

  • AXI Data Width— This parameter is the data bus width in bits. The IP supports 32 bits or 64 bits.

  • ID Width— This parameter is the ID width in bits. Its value must match the ID width of the AXI4 subordinate.

When the program is running on your FPGA board, you can create an AXI manager object using theaximanagerobject. To access the subordinate memory locations on the board, use thereadmemoryandwritememoryobject functions.

See Also

Related Examples

More About