Model Referencing for HDL Code Generation

Benefits of Model Referencing for Code Generation

Model referencing in your DUT subsystem enables you to:

Partition a large design into a hierarchy of smaller designs for reuse, modular development, and accelerated simulation.
Incrementally generate and test code.
HDL Coder™ incrementally generates code for referenced models according to theConfiguration Parameters dialog box>模型引用窗格>Rebuildoptions.
However, HDL Coder treatsIf any changes detected和If any changes in known dependencies detected和一样的。例如，如果您设置Rebuildto eitherIf any changes detected或者If any changes in known dependencies detected, HDL Coder regenerates code for referenced models only when the referenced models have changed.

How To Generate Code for a Referenced Model

By default,Generate VHDL code for model references into a single libraryis enabled. The VHDL code is generated in a single library instead of separate libraries. In this case, set theScalarizeports.property tooffbefore generating HDL code.

生成代码时，如果在接口两个或多个生成的VHDL时遇到在矢量端口之间的键入或命名冲突^®code modules, use theScalarizeports.property to generate non-conflicting port definitions. For more information, see标定港口.

You can generate HDL code for the referenced model using the UI or the command line.

使用UI.

Right-click the Model block and selectHDL Code>HDL Block Properties.
ForArchitecture, selectModelReference.
从DUT子系统生成HDL代码。

使用命令行

Set theArchitectureproperty of the Model block toModelReference. For example, for a DUT subsystem,mydut, that includes a model reference,参考_Model., enter this command:
```
hdlset_param（'mydut/referenced_model',...'建筑学','ModelReference');
```
Generate HDL code for your DUT subsystem.
```
makehdl ('mydut');
```

Generate Code for Model Arguments

To generate a single Verilog^®module或者VHDLentityfor instances of a referenced model with different model argument values, see为引用模型生成参数化代码.

Generate Comments

如果输入文本Model阻止属性对话框Descriptionfield, HDL Coder generates a comment in the HDL code.

Limitations

Model block must have default values for the Block parameters.
Model block cannot be a masked subsystem.
Multiple model references that refer to the same model must have the same HDL block properties.
引用的模型不能受到保护型号。
必须禁用分层分布式流水线。

HDL编码器无法在模型引用中移动寄存器。因此，引用的模型可以抑制这些优化：

Distributed pipelining
约束输出流水线
Streaming

When you have model references and generate HDL code, the generated model, validation model, and cosimulation model can fail to compile or simulate. To fix compilation or simulation errors, make sure that the referenced models are loaded or are on the search path.

The coder can apply the resource sharing optimization to share referenced model instances. However, you can apply this optimization only when all model references that point to the same referenced model have the same rate after optimizations and rate propagation. The model reference final rate may differ from the original rate, but all model references that point to the same referenced model must have the same final rate.