使用状态控制块与HDL编码™生成更高效的代码

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这个例子展示了如何使用国家控制块生成hardware-friendly HDL代码使用HDL编码器。

介绍了国家控制块

国家控制块是一块,修改仿真软件模拟行为包含子系统和所有子系统下面嵌套。金宝app其目的是为了更准确地模拟数字硬件时钟的同步行为,特别是对块状态和使用显式启用和复位信号。

当一个国家控制块放置在一个子系统,其参数设置为“同步”,生成的HDL代码将更多的硬件友好。当一个子系统是在同步模式下有一个图形在其左下角“S”。状态控制块的参数设置为“经典”的行为相同,当没有状态控制块的子系统。

仿真行为两种模式之间的区别很小,但是意义生成高效的HDL代码。的差异集中在模拟行为涉及明确的复位,使信号。例如,在同步模式下,显式块复位输入优先于块使输入信号。

经典模式行为与显式启用延迟输入端口

高密度脂蛋白HDL编码生成的代码模拟相同的模型,它是生成的。在经典的国家控制模式中,生成的代码对某些结构实现最优的硬件将这个需求。例如,延迟块与显式允许输入将生成一个旁路登记,由一个寄存器和多路复用器,除了建模登记,捕获模型经典模式的行为。金宝app

检查Enabled_Delay的内容。vhd观察额外信号和旁路注册登记。

load_system (“hdlcoder_statecontrol_model”);open_system (“hdlcoder_statecontrol_model”);set_param (“hdlcoder_statecontrol_model”,“SimulationCommand”,“更新”);makehdl (“hdlcoder_statecontrol_model / MAC冷杉块”,“TargetDirectory”,“hdlsrc_classic”);

# # #产生高密度脂蛋白“hdlcoder_statecontrol_model / MAC冷杉块”。使用的配置集模型# # # < a href = " matlab: configset。showParameterGroup (hdlcoder_statecontrol_model, {HDL代码生成的})" > hdlcoder_statecontrol_model < / > HDL代码生成参数。# # #“hdlcoder_statecontrol_model”高密度脂蛋白检查运行模型。# # #开始编译模型的“hdlcoder_statecontrol_model”……# # #应用高密度脂蛋白对模型优化“hdlcoder_statecontrol_model”……# # #开始生成模型。# # #模型生成完成。# # #开始硬件描述语言(VHDL)代码生成“hdlcoder_statecontrol_model”。# # #工作hdlcoder_statecontrol_model / MAC冷杉块/多项式系数ROM hdlsrc_classic / hdlcoder_statecontrol_model / Coeff_ROM.vhd。 ### Working on hdlcoder_statecontrol_model/MAC FIR Block/Enabled_Delay as hdlsrc_classic/hdlcoder_statecontrol_model/Enabled_Delay.vhd. ### Working on hdlcoder_statecontrol_model/MAC FIR Block/RAM delay line/circular buffer logic as hdlsrc_classic/hdlcoder_statecontrol_model/circular_buffer_logic.vhd. ### Working on hdlcoder_statecontrol_model/MAC FIR Block/RAM delay line/SimpleDualPortRAM_generic as hdlsrc_classic/hdlcoder_statecontrol_model/SimpleDualPortRAM_generic.vhd. ### Working on hdlcoder_statecontrol_model/MAC FIR Block/RAM delay line as hdlsrc_classic/hdlcoder_statecontrol_model/RAM_delay_line.vhd. ### Working on hdlcoder_statecontrol_model/MAC FIR Block as hdlsrc_classic/hdlcoder_statecontrol_model/MAC_FIR_Block.vhd. ### Generating package file hdlsrc_classic/hdlcoder_statecontrol_model/MAC_FIR_Block_pkg.vhd. ### Code Generation for 'hdlcoder_statecontrol_model' completed. ### Creating HDL Code Generation Check Report file:///tmp/Bdoc21b_1757077_221352/tp19d50da1/hdlsrc_classic/hdlcoder_statecontrol_model/MAC_FIR_Block_report.html ### HDL check for 'hdlcoder_statecontrol_model' complete with 0 errors, 0 warnings, and 0 messages. ### HDL code generation complete.

类型hdlsrc_classic / hdlcoder_statecontrol_model / Enabled_Delay.vhd

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -文件名称:hdlsrc_classic / hdlcoder_statecontrol_model / Enabled_Delay。vhd——创建:2021-09-01 16:30:47——由MATLAB 9.11和高密度脂蛋白编码器3.19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -模块:Enabled_Delay——源路径:hdlcoder_statecontrol_model / MAC冷杉块/ Enabled_Delay——等级水平:1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -库IEEE;使用IEEE.std_logic_1164.ALL;使用IEEE.numeric_std.ALL;实体Enabled_Delay端口(std_logic clk:;重置:std_logic;在std_logic enb:;din_re: std_logic_vector(33报纸0);——sfix34_En31 din_im: std_logic_vector(33报纸0);——sfix34_En31 LocalEnable: std_logic; Out1_re : OUT std_logic_vector(33 DOWNTO 0); -- sfix34_En31 Out1_im : OUT std_logic_vector(33 DOWNTO 0) -- sfix34_En31 ); END Enabled_Delay; ARCHITECTURE rtl OF Enabled_Delay IS -- Signals SIGNAL din_re_signed : signed(33 DOWNTO 0); -- sfix34_En31 SIGNAL din_im_signed : signed(33 DOWNTO 0); -- sfix34_En31 SIGNAL Enabled_Delay_bypass_delay_re : signed(33 DOWNTO 0); -- sfix34_En31 SIGNAL Enabled_Delay_bypass_delay_im : signed(33 DOWNTO 0); -- sfix34_En31 SIGNAL Enabled_Delay_reg_re : signed(33 DOWNTO 0); -- sfix34_En31 SIGNAL Enabled_Delay_reg_im : signed(33 DOWNTO 0); -- sfix34_En31 SIGNAL dout_re : signed(33 DOWNTO 0); -- sfix34_En31 SIGNAL dout_im : signed(33 DOWNTO 0); -- sfix34_En31 BEGIN din_re_signed <= signed(din_re); din_im_signed <= signed(din_im); Enabled_Delay_1_process : PROCESS (clk, reset) BEGIN IF reset = '1' THEN Enabled_Delay_bypass_delay_re <= to_signed(0, 34); Enabled_Delay_bypass_delay_im <= to_signed(0, 34); Enabled_Delay_reg_re <= to_signed(0, 34); Enabled_Delay_reg_im <= to_signed(0, 34); ELSIF clk'EVENT AND clk = '1' THEN IF enb = '1' AND LocalEnable = '1' THEN Enabled_Delay_bypass_delay_im <= Enabled_Delay_reg_im; Enabled_Delay_reg_im <= din_im_signed; Enabled_Delay_bypass_delay_re <= Enabled_Delay_reg_re; Enabled_Delay_reg_re <= din_re_signed; END IF; END IF; END PROCESS Enabled_Delay_1_process; dout_re <= Enabled_Delay_reg_re WHEN LocalEnable = '1' ELSE Enabled_Delay_bypass_delay_re; dout_im <= Enabled_Delay_reg_im WHEN LocalEnable = '1' ELSE Enabled_Delay_bypass_delay_im; Out1_re <= std_logic_vector(dout_re); Out1_im <= std_logic_vector(dout_im); END rtl;

同步模式行为与显式启用延迟输入端口

延迟块与显式启用同步状态控制模式将产生HDL代码创建更有效的硬件。实现不包含绕过寄存器。

检查Enabled_Delay_Sync。vhd和注意改善在生成的代码与经典模式的输出。

makehdl (“hdlcoder_statecontrol_model / MAC冷杉块同步”,“TargetDirectory”,“hdlsrc_sync”);

# # #产生高密度脂蛋白的hdlcoder_statecontrol_model / MAC冷杉块同步。使用的配置集模型# # # < a href = " matlab: configset。showParameterGroup (hdlcoder_statecontrol_model, {HDL代码生成的})" > hdlcoder_statecontrol_model < / > HDL代码生成参数。# # #“hdlcoder_statecontrol_model”高密度脂蛋白检查运行模型。# # #开始编译模型的“hdlcoder_statecontrol_model”……# # #应用高密度脂蛋白对模型优化“hdlcoder_statecontrol_model”……# # #开始生成模型。# # #模型生成完成。# # #开始硬件描述语言(VHDL)代码生成“hdlcoder_statecontrol_model”。# # #工作hdlcoder_statecontrol_model / MAC冷杉块同步/多项式系数ROM hdlsrc_sync / hdlcoder_statecontrol_model / Coeff_ROM.vhd。 ### Working on hdlcoder_statecontrol_model/MAC FIR Block Sync/Enabled Delay Sync as hdlsrc_sync/hdlcoder_statecontrol_model/Enabled_Delay_Sync.vhd. ### Working on hdlcoder_statecontrol_model/MAC FIR Block Sync/RAM delay line/circular buffer logic as hdlsrc_sync/hdlcoder_statecontrol_model/circular_buffer_logic.vhd. ### Working on hdlcoder_statecontrol_model/MAC FIR Block Sync/RAM delay line/SimpleDualPortRAM_generic as hdlsrc_sync/hdlcoder_statecontrol_model/SimpleDualPortRAM_generic.vhd. ### Working on hdlcoder_statecontrol_model/MAC FIR Block Sync/RAM delay line as hdlsrc_sync/hdlcoder_statecontrol_model/RAM_delay_line.vhd. ### Working on hdlcoder_statecontrol_model/MAC FIR Block Sync as hdlsrc_sync/hdlcoder_statecontrol_model/MAC_FIR_Block_Sync.vhd. ### Generating package file hdlsrc_sync/hdlcoder_statecontrol_model/MAC_FIR_Block_Sync_pkg.vhd. ### Code Generation for 'hdlcoder_statecontrol_model' completed. ### Creating HDL Code Generation Check Report file:///tmp/Bdoc21b_1757077_221352/tp19d50da1/hdlsrc_sync/hdlcoder_statecontrol_model/MAC_FIR_Block_Sync_report.html ### HDL check for 'hdlcoder_statecontrol_model' complete with 0 errors, 0 warnings, and 0 messages. ### HDL code generation complete.

类型hdlsrc_sync / hdlcoder_statecontrol_model / Enabled_Delay_Sync.vhd

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -文件名称:hdlsrc_sync / hdlcoder_statecontrol_model / Enabled_Delay_Sync。vhd——创建:2021-09-01 16:30:59——由MATLAB 9.11和高密度脂蛋白编码器3.19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -模块:Enabled_Delay_Sync——源路径:hdlcoder_statecontrol_model / MAC冷杉块同步/启用延迟同步——层次水平:1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -库IEEE;使用IEEE.std_logic_1164.ALL;使用IEEE.numeric_std.ALL;实体Enabled_Delay_Sync端口(std_logic clk:;重置:std_logic;在std_logic enb:;din_re: std_logic_vector(33报纸0);——sfix34_En31 din_im: std_logic_vector(33报纸0);——sfix34_En31 LocalEnable: std_logic; Out1_re : OUT std_logic_vector(33 DOWNTO 0); -- sfix34_En31 Out1_im : OUT std_logic_vector(33 DOWNTO 0) -- sfix34_En31 ); END Enabled_Delay_Sync; ARCHITECTURE rtl OF Enabled_Delay_Sync IS -- Signals SIGNAL din_re_signed : signed(33 DOWNTO 0); -- sfix34_En31 SIGNAL din_im_signed : signed(33 DOWNTO 0); -- sfix34_En31 SIGNAL dout_re : signed(33 DOWNTO 0); -- sfix34_En31 SIGNAL dout_im : signed(33 DOWNTO 0); -- sfix34_En31 BEGIN din_re_signed <= signed(din_re); din_im_signed <= signed(din_im); Enabled_Delay_process : PROCESS (clk, reset) BEGIN IF reset = '1' THEN dout_re <= to_signed(0, 34); dout_im <= to_signed(0, 34); ELSIF clk'EVENT AND clk = '1' THEN IF enb = '1' AND LocalEnable = '1' THEN dout_re <= din_re_signed; dout_im <= din_im_signed; END IF; END IF; END PROCESS Enabled_Delay_process; Out1_re <= std_logic_vector(dout_re); Out1_im <= std_logic_vector(dout_im); END rtl;

启用子系统

当一个模型有一个启用子系统在同步模式下,生成的代码也将得到改善。同步模式使子系统将不再生成绕过注册子系统输出。此外,任何寄存器内的子系统启用显式启用输入也会显示前面所讨论的改进一样。

MATLAB函数块和同步模式

MATLAB函数块需要更精确的配置以用于同步模式。如果块包含一个直接从块组合路径输入输出,必须启用额外的设置。

MATLAB将来发布的编辑数据菜单中选择打开MATLAB功能块端口和数据管理器。每个块包含一个组合输出路径必须标记为允许直接引线。

此设置允许代码生成从MATLAB功能块在同步模式下,当组合和连续路径的代码块。

open_system (“hdlcoder_statecontrol_model / MAC冷杉块同步/ RAM延迟线的)open_system (“hdlcoder_statecontrol_model / MAC冷杉块同步/ RAM延迟线/循环缓冲逻辑”)

额外的信息

更多地了解国家控制块,请参考文档。