Run a Design Error Detection Analysis

Workflow for Detecting Design Errors

To analyze your model for design errors, use the following workflow:

Verify that your model is compatible with金宝app^®Design Verifier™software.
If you have Stateflow^®objects in your model, in the Configuration Parameters dialog box, on theDiagnostics>Stateflow窗格中,设置Unreachable execution pathtoerror.
Specify options that control howSimulink Design Verifierdetects design errors in your model.
Execute theSimulink Design Verifieranalysis.
Review the analysis results.

Note

If you select design error detection for dead logic, you cannot select any other type of design error detection. For dead logic detection,Simulink Design Verifierperforms an independent analysis. If you want to detect design errors for dead logic and any of the other types of design errors, you must perform design error detection analysis twice.

Understand the Analysis Results

When you run a design error detection analysis, by default, the software highlights model objects in one of four colors so that the analysis results are easy to review.

Model Object Highlighting Color	Analysis Results
Green	One of the following: The analysis did not find overflow or division-by-zero errors. The analysis did not find dead logic. The analysis did not find intermediate or output signals outside the range of user-specified minimum and maximum constraints. The analysis did not find out of bound array access errors. Note If your design contains at least one object thatSimulink Design Verifierhighlights red, other objects in your model that are highlighted green may also contain further design errors. If an object in your design causes run-time errors,Simulink Design Verifiermay not be able to determine further errors on objects that are downstream of or rely on the results of the object that causes the run-time errors. Resolve the errors that cause the initial red highlighting and re-run the analysis to determine ifSimulink Design Verifierwill also highlight other objects in your model as red.
Red	One of the following: The analysis found at least one test case that causes overflow or division-by-zero errors. The analysis found dead logic. The analysis found intermediate or output signals outside the range of user-specified minimum and maximum constraints. The analysis found at least one test case that causes an out of bound array access error.
Orange	For at least one objective, the analysis could not determine if the model has dead logic, overflow errors, division-by-zero errors, signals outside the user-specified range, or out of bound array access errors. This situation can occur when: The analysis times out. The software cannot determine if an error occurred or not. This result is due to: Automatic stubbing errors; for more information, seeHandle Incompatibilities with Automatic Stubbing. 分析引擎的限制。
Gray	The model object was not part of the analysis.

TheSimulink Design VerifierResults window initially displays a summary of the analysis results, as in the following example.

When you click an object in the model, additional details about the results for that object are displayed in theSimulink Design VerifierResults window.

Tip

By default, theSimulink Design VerifierResults window is always the topmost visible window. To change that setting, click theicon and on the context menu, clear the check mark next toAlways on top.

Review the Latest Analysis Results in the Results Summary Window

If you close the analysis results to fix the cause of the errors in your model, you might need to rereview the analysis results. As long as your model remains open, you can view the results of your most recent analysis results in the Results Summary Window.

After you close your model, you can no longer view any analysis results.

To view the latest results, on theDesign Verifiertab, in theReview Resultssection, clickResults Summary.

For anySimulink Design Verifieranalysis, from the Results Summary Window, you can perform the following tasks:

Highlight the analysis results on the model.
Generate a detailed analysis report.
Create the harness model, or if the harness model already exists, open it.

Note

If no objectives are falsified, you cannot create the harness model.
查看数据文件。
View the log file.

Check For Design Errors using the Model Advisor

You can perform design error detection analysis from the Model Advisor, which is particularly useful if you need to perform other model checks. To analyze your model from the Model Advisor, follow this high-level workflow:

Specify options that control howSimulink Design Verifierdetects design errors in your model.
Open the Model Advisor.
From the system hierarchy, select the model or model component you want to analyze
Expand the design error detection analysis items. Look for Simulink Design Verifier under eitherBy ProductorBy Task.
If you have not checked your model for compatibility, enable the compatibility check for Simulink Design Verifier.
Select the design error detection checks you want to run.
Run the selected checks.
Review the analysis results.