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IntelSoC Devices

Generate and deploy HDL code and embedded software on Intel®SoC Devices

HDL Coder™ can generate an IP core, integrate it into your Qsys project, and program the Intel hardware. Using Embedded Coder®, you can generate and build the embedded software, and run it on the ARM®processor. SeeHardware-Software Co-Design Workflow for SoC Platforms.

To deploy your design to the Intel SoC device, you must install theHDL Coder Support Package for Intel SoC Devices. For installation information, seeHDL Coder Supported Hardware.

Classes

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hdlcoder.Board Board registration object that describes SoC custom board
hdlcoder.WorkflowConfig Configure HDL code generation and deployment workflows
hdlcoder.ReferenceDesign 参考设计登记对象描述s SoC reference design

Functions

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socExportReferenceDesign Export custom reference design for HDL Workflow Advisor
addExternalIOInterface Define external IO interface for board object
addExternalPortInterface Define external port interface for board object
addInternalIOInterface Add and define internal IO interface between generated IP core and existing IP cores
addAXI4MasterInterface Add and define AXI4 Master interface
addAXI4SlaveInterface Add and define AXI4 slave interface
addAXI4StreamInterface Add AXI4-Stream interface
addAXI4StreamVideoInterface Add AXI4-Stream Video interface
addClockInterface Add clock and reset interface
addCustomEDKDesign SpecifyXilinxEDK MHS project file
addCustomQsysDesign SpecifyAlteraQsys project file
addCustomVivadoDesign SpecifyXilinxVivadoexported block design Tcl file
addIPRepository Include IP modules from your IP repository folder in your custom reference design
addParameter Add and define custom parameters for your reference design
validateReferenceDesign Check property values in reference design object
validateBoard Check property values in board object
CallbackCustomProgrammingMethod Function handle for custom callback function that gets executed during Program Target Device task in the Workflow Advisor
EmbeddedCoderSupportPackage Specify whether to use anEmbedded Codersupport package
PostBuildBitstreamFcn Function handle for callback function that gets executed after Build FPGA Bitstream task in the HDL Workflow Advisor
PostCreateProjectFcn Function handle for callback function that gets executed after Create Project task in the HDL Workflow Advisor
PostSWInterfaceFcn Function handle for custom callback function that gets executed after Generate Software Interface task in the HDL Workflow Advisor
PostTargetInterfaceFcn Function handle for callback function that gets executed after Set Target Interface task in the HDL Workflow Advisor
PostTargetReferenceDesignFcn Function handle for callback function that gets executed after Set Target Reference Design task in the HDL Workflow Advisor

Topics

Related Information

Troubleshooting

Resolve Timing Failures in IP Core Generation and Simulink Real-Time FPGA I/O Workflows

Resolve timing failures in Build FPGA Bitstream step of IP Core Generation Workflow or Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards.