If Action Subsystem

Subsystem whose execution is enabled by If block

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Libraries:
Simulink / Ports & Subsystems

Description

TheIf Action Subsystemblock is aSubsystemblock preconfigured as a starting point for creating a subsystem whose execution is controlled by anIfblock. TheIfblock evaluates a logical expression and then, depending on the result of the evaluation, outputs an action signal. Execution of the subsystem is controlled by anAction Portblock placed inside the subsystem.

金宝app^®ignores a priority set on anIf Action Subsystemblock. Instead, set the priority on theIfblock that initiates execution of the subsystem.

Merge Signals from If Action Subsystem Blocks

This example shows how to merge signals controlled by anIfblock. For more information, seeSelect Subsystem Execution.

Model ex_if_block

TheIfblock selects the execution of anIf Action Subsystemblock from a set of subsystems. Regardless of which subsystem theIfblock selects, you can create one output signal with aMergeblock.

All blocks in anIf Action Subsystemblock must execute at the same rate as the driving If block. To satisfy this requirement, set the sample time parameter for each block to either inherited (-1) or the same value as the If block sample time.

Support for Fixed-Point Data Type

TheIf不直接支持定点数据块t金宝appypes. However, you can use theCompare To Constantblock to work around this limitation. For more information,Fixed-Point Data Type Support for If Block.

Examples

Simulink Subsystem Semantics

This set of examples shows different types of Simulink® Subsystems and what semantics are used when simulating these Subsystems. Each example provides a description of the model and the subtleties governing how it will be executed.

Open Model

If-Then-Else Blocks

The effect of feeding a sine wave into If Action Subsystem blocks. It is designed to illustrate the similarity between the If Action Subsystem block and the Enabled Subsystem block.

Open Model

Modeling Clutch Lock-Up Using If Blocks

Use If/Else subsystems to build a clutch model. An 'If' subsystem models the clutch dynamics in the locked position while an 'Else' subsystem models the unlocked position. One or the other is enabled using the 'If' block. The dot-dashed lines from the 'If' block denote control signals, which are used to enable If/Else (or other conditional) subsystems. Checking any of the boxes on the GUI produces a plot of any of the selected variables (versus time).

Open Model

Ports

Input

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In—Signal input to a subsystem block
scalar | vector | matrix

Placing anInportblock in a subsystem block adds an external input port to the block. The port label matches the name of theInportblock.

UseInportblocks to get signals from the local environment.

Action—Control signal input to a subsystem block
scalar | vector | matrix

Placing anAction Portblock in a subsystem block adds an external input port to the block and changes the block to anIf Action Subsystem.

Dot-dash lines from aSwitch Caseblock to anSwitch Case Action Subsystemblock representactionsignals. An action signal is a control signal connected to the action port of a Switch Case Action Subsystem block. A message on the action signal initiates execution of the subsystem.

Data Types:action

Output

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Out—Signal output from a subsystem
scalar | vector | matrix

Placing anOutportblock in a subsystem block adds an output port from the block. The port label on the subsystem block is the name of theOutportblock.

UseOutportblocks to send signals to the local environment.

Block Characteristics

Data Types	`Boolean^a`\|`bus^a`\|`double^a`\|`enumerated^a`\|`fixed point^a`\|`一半^a`\|`integer^a`\|`single^a`\|`string^a`
Direct Feedthrough	`no`
Multidimensional Signals	`yes^a`
Variable-Size Signals	`yes^a`
Zero-Crossing Detection	`no`
^aActual data type or capability support depends on block implementation.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Actual code generation support depends on block implementation.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

Best Practices

When using If Action Subsystems in models targeted for HDL code generation, it is good practice to consider the following:

Specify a initial output value for the outports in the If Action Subsystem. You can initialize the output value for the Outport blocks by using one of these methods:
- Specify a numeric value to theInitial outputblock parameter of the Outport blocks.
- Inherit initial output values from input signals connected to the Outport blocks. For more information, seeConditional Subsystem Initial Output Values.
For HDL code generation, the valid input signal to the Outport blocks for setting initial output values include:
- Output ports from another conditionally executed subsystem
- Constant blocks

HDL Architecture

Architecture Description

Module(default) Generate code for the subsystem and the blocks within the subsystem.

Architecture	Description
`Module`(default)	Generate code for the subsystem and the blocks within the subsystem.
`BlackBox`	Generate a black box interface. The generated HDL code includes only the input/output port definitions for the subsystem. Therefore, you can use a subsystem in your model to generate an interface to existing, manually written HDL code. The black-box interface generation for subsystems is similar to the Model block interface generation without the clock signals.
`No HDL`	Remove the subsystem from the generated code. You can use the subsystem in simulation, however, treat it as a “no-op” in the HDL code.

BlackBox

Generate a black box interface. The generated HDL code includes only the input/output port definitions for the subsystem. Therefore, you can use a subsystem in your model to generate an interface to existing, manually written HDL code.

The black-box interface generation for subsystems is similar to the Model block interface generation without the clock signals.

No HDL

Remove the subsystem from the generated code. You can use the subsystem in simulation, however, treat it as a “no-op” in the HDL code.

HDL Block Properties

General
AdaptivePipelining	Automatic pipeline insertion based on the synthesis tool, target frequency, and multiplier word-lengths. The default is`inherit`. See alsoAdaptivePipelining(HDL Coder).
BalanceDelays	Detects introduction of new delays along one path and inserts matching delays on the other paths. The default is`inherit`. See alsoBalanceDelays(HDL Coder).
ClockRatePipelining	Insert pipeline registers at a faster clock rate instead of the slower data rate. The default is`inherit`. See alsoClockRatePipelining(HDL Coder).
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is`0`. For more details, seeConstrainedOutputPipeline(HDL Coder).
DistributedPipelining	Pipeline register distribution, or register retiming. The default is`inherit`. See alsoDistributedPipelining(HDL Coder).
DSPStyle	Synthesis attributes for multiplier mapping. The default is`none`. See alsoDSPStyle(HDL Coder).
FlattenHierarchy	Remove subsystem hierarchy from generated HDL code. The default is`inherit`. See alsoFlattenHierarchy(HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is`0`. For more details, seeInputPipeline(HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is`0`. For more details, seeOutputPipeline(HDL Coder).
SharingFactor	Number of functionally equivalent resources to map to a single shared resource. The default is 0. See alsoResource Sharing(HDL Coder).
StreamingFactor	Number of parallel data paths, or vectors, that are time multiplexed to transform into serial, scalar data paths. The default is 0, which implements fully parallel data paths. See alsoStreaming(HDL Coder).

Target Specification

This block cannot be the DUT, so the block property settings in theTarget Specificationtab are ignored.

Restrictions

If the output of the subsystem is a bus thenInitial Outputof the outport must be 0.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Actual data type support depends on block implementation.

版本历史

Introduced before R2006a

If Action Subsystem

Description