Logic Analyzer
随着时间的流逝,可视化,测量和分析过渡和状态
打开逻辑分析仪应用程序
在Simuli金宝appnk工具条模拟选项卡上,单击Logic Analyzer应用按钮。如果未显示按钮,请扩展评论结果应用程序库。您最新的数据可视化选择可以在Simulink会话中保存。金宝app
To visualize referenced models, you must open the Logic Analyzer from the referenced model. You should see the name of the referenced model in the Logic Analyzer toolbar.
Examples
相关示例
- 使用逻辑分析仪检查和测量过渡
- 可视化多个信号使用逻辑分析仪
- 部分串行收缩期FIR滤波器实现(DSP HDL Toolbox)
- Fully Parallel Systolic FIR Filter Implementation(DSP HDL Toolbox)
- FPGA的可编程FIR过滤器(HDL编码器)
- 状态和数据的日志仿真输出(状态流)
- 查看逻辑分析仪中的状态流状态(状态流)
- Configure Logic Analyzer
Limitations
Logging Settings
If you enable the configuration parameterLog Dataset data to file(金宝appSimulink),,,,you cannot stream logged data to theLogic Analyzer。
标记用于记录的信号
Simulink.sdi.markSignalForStreaming
(金宝appSimulink)或用仪表板范围(金宝appSimulink)do not appear on theLogic Analyzer。You cannot visualize数据存储存储器(金宝appSimulink)block signals in theLogic Analyzerif you set the日志数据存储数据parameter to on.
Input Signal Limitations
信号s marked for logging for theLogic Analyzermust have fewer than 8000 samples per simulation step.
这Logic Analyzerdoes not support frame-based processing.
对于64位整数和大于53位的固定点数,如果数字大于双精度的最大值,则数字之间的过渡可能无法正确显示。
You may see performance degradation in theLogic Analyzerfor large matrices (greater than 500 elements) and buses with more than 1000 signals.
这Logic Analyzer不支持状态流数据输金宝app出。
Graphical Settings
在运行仿真时,您不能缩放,锅锅或修改触发器。
要可视化恒定信号,在设置中,您必须设置Formatto
Digital
。Constants marked for logging are visualized as a continuous transition.
Mode | Supported | Notes and Limitations |
---|---|---|
Normal |
Yes |
|
Accelerator |
Yes |
你不能使用Logic Analyzer可视化信号Model(金宝appSimulink)blocks withSimulation mode设置 |
Rapid Accelerator |
Yes |
数据在Logic Analyzer在模拟过程中。 If you simulate a model with the simulation mode set to rapid accelerator, after simulation the following signals cannot be visualized in theLogic Analyzer:
|
Processor-in-the-loop (PIL) |
No |
|
Software-in-the-loop (SIL) |
No |
|
外部的 |
No |
有关这些模式的更多信息,请参阅How Acceleration Modes Work(金宝appSimulink)。