Bit Clear

Set specified bit of stored integer to zero

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库:
Simulink / Logic and Bit Operations
HDL Coder / Logic and Bit Operations

Description

The Bit Clear block sets the specified bit, given by its index, of the stored integer to zero. Scaling is ignored.

您可以使用该位指定要设置为零的位Index of bitparameter, where bit zero is the least significant bit.

Ports

The Bit Clear block supports Simulink^®强度ger, fixed-point, and Boolean data types. The block does not support true floating-point data types or enumerated data types.

Input

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`Port_1`— Input signal
scalar or vector

The input signal is the specified bit of the stored integer.

Data Types:single|double|Boolean|固定点

Output

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`Port_1`— Output signal
scalar or vector

The output consists of the specified bit set to zero.

Data Types:single|double|int8|int16|int32|int64|uint8|uint16|uint32|uint64|Boolean|固定点|enumerated|bus

Parameters

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`Index of bit`— Index of bit
0 (default) | scalar or vector

Index of bit where bit 0 is the least significant bit.

Programmatic Use

Block Parameter:我咬

Type: scalar or vector

Values: {'0'}

Default: '0'

Model Examples

Using a Bit Clear block

If the Bit Clear block is turned on for bit 2, bit 2 is set to 0.

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Block Characteristics

Data Types	`Boolean^[a]`\|`固定点`\|`强度ger`
Direct Feedthrough	`yes`
Multidimensional Signals	`yes`
Variable-Size Signals	`no`
Zero-Crossing Detection	`no`
^[a]Bit operations are not recommended for use with Boolean signals.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is`0`。有关更多详细信息，请参阅ConstrainedOutputPipeline(HDL Coder)。
InputPipeline	输入管道级的数量以插入生成的代码。分布式流水线和约束输出流水线可以移动这些寄存器。默认为`0`。有关更多详细信息，请参阅InputPipeline(HDL Coder)。
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is`0`。有关更多详细信息，请参阅OutputPipeline(HDL Coder)。

Bit Clear

Description

Ports

Input

`Port_1`— Input signal
scalar or vector

Output

`Port_1`— Output signal
scalar or vector

Parameters

`Index of bit`— Index of bit
0 (default) | scalar or vector

Programmatic Use

Model Examples

Using a Bit Clear block

Block Characteristics

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

See Also

Simulink Documentation

金宝app

Model-Based Design for Embedded Control Systems

Bit Clear

Description

Ports

Input

Port_1— Input signalscalar or vector

Output

Port_1— Output signalscalar or vector

Parameters

Index of bit— Index of bit0 (default) | scalar or vector

Programmatic Use

Model Examples

Using a Bit Clear block

Block Characteristics

Extended Capabilities

C/C++ Code GenerationGenerate C and C++ code using Simulink® Coder™.

HDL Code GenerationGenerate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code GenerationGenerate Structured Text code using Simulink® PLC Coder™.

Fixed-Point ConversionDesign and simulate fixed-point systems using Fixed-Point Designer™.

See Also

Simulink Documentation

金宝app

Model-Based Design for Embedded Control Systems

`Port_1`— Input signal
scalar or vector

`Port_1`— Output signal
scalar or vector

`Index of bit`— Index of bit
0 (default) | scalar or vector

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.