哈里斯加速验证of Signal Processing FPGAs

Challenge

Streamline a time-consuming manual process for testing signal processing FPGA implementation

Solution

Use HDL Verifier to verify the HDL design from within MATLAB

Results

功能验证时间缩短了85％以上
100％计划的测试用例已完成
Design implemented defect-free

“HDL Verifier provided a direct cosimulation interface between our MATLAB model and our logic simulator, which enabled us to verify our design earlier, identify problems faster, complete more tests, and compress our entire development cycle.”
Jason Plew, Harris Corporation

基于Harris FPGA的系统。

Engineers at Harris Corporation are accustomed to delivering sophisticated FPGA-based signal processing systems within tight schedules. To meet their customers’ often stringent requirements and their own quality standards, the engineers thoroughly verify the HDL design of each system before it is synthesized.

In the past, HDL verification required several manual steps. Harris engineers have automated the process by using HDL Verifier™在MATLAB之间提供双向联系^®系统模型和HDL设计模拟以节奏模拟^®Incisive^®. The new process eliminates ambiguity between the algorithm specification and HDL verification, reduces duplication of effort, and improves communication between system and HDL engineers.

Harris的高级工程师Jason Plew说：“与MATLAB和HDL验证者进行共同拟合不仅使在子系统级别进行模拟变得更加容易，还使我们能够更加完全验证整个系统。”“我们大大减少了开发子系统测试台所需的时间，这使我们能够更早地验证和调试设计。”

Challenge

Harris engineers needed to design and verify a signal processing system that spanned multiple Xilinx^®Virtex^®FPGA。在这个劳动密集型过程中，一旦模拟了子系统的定点模型，团队将导出包含刺激数据的大型文本文件和这些模拟的预期结果，并将其导入了Cadence cincisive。然后，一位经验丰富的工程师在HDL中编写了测试台以读取数据，应用刺激并验证结果。如果结果不匹配，则团队必须深入研究大规模的结果文件，以找出模拟失败的位置和原因。对于测试特性的每一次更改，他们必须重新出而eNTORPORT，这需要8个小时的乏味的手动工作。

“We spent a considerable amount of time churning through manual steps for each subsystem, and as a result, we only had time to complete 30% of the desired system-level test cases before our deadline,” Plew recalls.

Harris needed a way to drive the input signals in the logic simulator directly, eliminating the need to write the HDL test benches and the overhead of managing huge text files of test data.

Solution

Harris工程师在MATLAB中对其信号处理系统进行了建模和模拟。MATLAB模型成为可重复使用的测试台，它们可以使用HDL验证器进行交互方式与其cadence尖锐模拟器进行共同审核。

使用MATLAB和DSP系统工具箱™，工程师开发了基本信号处理数据路径的理想浮点模型，他们用来验证设计满足功能要求。

将模型转换为固定点后，他们优化了在硬件中实现的算法。在MATLAB中进行了其他模拟，以确保在规格内执行的定点实现。

Using the fixed-point model as an executable specification, Harris engineers then implemented the system in HDL.

The team used HDL Verifier to enable the MATLAB code to act as the test bench for the implementation. Via the cosimulation interface, MATLAB was used to supply stimulus to and analyze the results from the HDL simulation.

为了加快多个测试用例的执行，Harris Engineers开发了一个MATLAB控制脚本，该脚本在Linux Computing网格上管理了多个并行的共同点。

The team used this approach to rapidly verify individual subsystems as well as the overall signal processing chain before synthesizing and successfully demonstrating the device. Harris engineers have begun applying the same approach on other projects, including one that requires a million-point fast Fourier transform.

Results

功能验证时间缩短了85％以上. “It used to take an experienced engineer about 8 hours to prepare a subsystem test bench,” says Plew. “With HDL Verifier, we can create one in an hour, and because MATLAB generates the stimulus and performs the analysis, we have all the test results ready in MATLAB for postprocessing.”

100％计划的测试用例已完成. “Our previous process was so complex that we often performed little verification at the subsystem level, and our schedule kept us from running more than 30% of the desired test cases at the system level,” says Plew. “With MathWorks tools, we generated and simulated 100% of those test cases using an automated process that enables us to find most defects at the subsystem level.”

Design implemented defect-free. “We eliminated weeks of lab debug time because we had so thoroughly verified the design by using HDL Verifier to cosimulate our HDL code in MATLAB and Cadence Incisive,” Plew notes. “In fact, the data path elements of the FPGA performed as designed right from the start.”

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