Deployment

创建包含用户编程的比特流并将其下载到FPGA硬件

To program the FPGA and run your algorithm on the hardware, HDL Coder™ can generate an IP core, and deploy it to the Xilinx^®FPGA boards. You can also program the FPGA board by using the FPGA Turnkey workflow, which generates HDL code for your algorithm and the FPGA top level wrapper and then deploys your design to the board.

Topics

IP Core Generation

IP Core Generation Workflow for Xilinx FPGA Boards
Learn how to use the IP Core Generation workflow with standalone FPGA devices and embed the IP core into the reference design.
Default System Reference Design
了解系统默认参考性用途e design and using the reference design.

FPGA Turnkey

Program Standalone Xilinx FPGA Development Board from Simulink
This example shows how to target a Xilinx FPGA development board for synthesis using the FPGA Turnkey workflow.
Program Standalone Xilinx FPGA Development Board from MATLAB
FPGA Turnkey workflow for deployment to standalone FPGA hardware.

Featured Examples

Access DUT Registers on Xilinx Pure FPGA Board Using IP Core Generation Workflow

Use the HDL Coder™ IP core generation workflow to develop reference designs for Xilinx® parts that do not use an embedded ARM® processor present but that still utilize the HDL Coder generated AXI interface to control the design under test (DUT). This example uses the HDL Verifier™ AXI Manager IP to access the HDL Coder generated DUT registers by enabling the reference design parameter optionInsert JTAG AXI Manager. You can then access DUT registers from MATLAB® directly. Alternatively, you can use the Xilinx JTAG AXI Master to access the DUT registers using Vivado® Tcl console by writing Tcl commands. For the Xilinx JTAG AXI Master, you must create a custom reference design. The FPGA design is implemented on the Xilinx Kintex®-7 KC705 board.

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IP Core Generation Workflow with a MicroBlaze processor: Xilinx Kintex-7 KC705

Use the HDL Coder™ IP Core Generation Workflow to develop reference designs for Xilinx® parts without an embedded ARM® processor present, but which still utilize the HDL Coder™ generated AXI interface to control the DUT. Specifically, this example will use the Xilinx Kintex-7 KC705 board and a MicroBlaze™ soft processor running a LightWeightIP (lwIP) based TCP/IP firmware server in the reference design to access the HDL Coder™ generated DUT registers from anywhere on the connected network. Further, this example will also highlight the difference between accessing data from a collection of registers implemented as multiple scalar ports and a collection of registers implemented as a single vector port.

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