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Generate Test Bench and Enable Code Coverage Using the HDL Workflow Advisor

The HDL Workflow Advisor guides you through the stages of generating HDL code for a Simulink®subsystem and the FPGA design process, such as:

  • Checking the model for HDL code generation compatibility and automatically fixing incompatible settings.

  • Generation of HDL code, a test bench, and scripts to build and run the code and test bench.

  • Generation of cosimulation or SystemVerilog DPI test benches and code coverage (requires HDL Verifier™).

  • Synthesis and timing analysis through integration with third-party synthesis tools.

  • Back-annotation of the model with critical path information and other information obtained during synthesis.

  • Complete automated workflows for selected FPGA development target devices, including FPGA-in-the-loop simulation (requires HDL Verifier), and theSimulink Real-Time™FPGA的I / O工作流。

To select test bench and code coverage options for generating HDL code from a Simulink model using the HDL Workflow Advisor:

  1. Perform the setup steps inSimulink模型的HDL代码生成和FPGA合成金宝app.

  2. In Step 3.1.4 of the HDL Workflow Advisor,Set Testbench Options中,选择test bench and code coverage options from theTest Bench Generation Output部分。该编码器为您的测试替补和运行脚本生成一个构建和运行脚本Simulation toolyou specify. If you select multiple test bench options, the coder generates one test bench and script for each type of test bench selected. If you selectHDL code coverage，测试台脚本打开生成的HDL代码的代码覆盖范围。有关不同类型的测试长椅的更多信息，请参阅Choose a Test Bench for Generated HDL Code. After you select your test bench options, clickApply.

  3. In Step 3.2,Generate RTL Code and Testbench中,选择Generate test bench. ClickApply，然后单击Run This Task. The coder generates HDL code for your subsystem, and the test benches and scripts you selected in step 3.1.3.

    • If you selectedCosimulation model, then step 3.3,Verify with HDL Cosimulation, appears in the HDL Workflow Advisor. This step automatically runs the generated cosimulation model. The model compares the result of the HDL code running in your HDL simulator with the output of your Simulink subsystem.

    • If you selectedHDL test bench, the coder generates a compile script,subsystemname_tb_compile, and a run script,subsystemname_tb_sim. The script file extension depends on your selected simulator. For example, at the command line in the Mentor Graphics®模特明®simulator, change to thehdl_prj/hdlsrc/modelnamefolder and run these commands:

      do symmetric_fir_compile.do do symmetric_fir_tb_compile.do do symmetric_fir_tb_sim.do

    • If you selectedSystemVerilog DPI测试台, the coder generates a script file,subsystemname_dpi_tb., that compiles the HDL code and runs the test bench simulation. The script file extension depends on your selected simulator. For example, at the command line in the Mentor Graphics ModelSim simulator, change to thehdl_prj/hdlsrc/modelnamefolder and run this command:

      do symmetric_fir_dpi_tb.do

    • If you selectedHDL code coverage, the code coverage report from running any test bench, including the cosimulation model, is saved inhdl_prj\hdlsrc\modelname\covhtmlreport.

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