Results Interpretation and Use

Log and review analysis results, generate report, create test harness model

You use金宝app^®Design Verifier™to log and review analysis results and generate analysis reports. You can generate test inputs and export them to new test cases inSimulink Test™.

Functions

`sldvloadresults`	Load Simulink Design Verifier analysis results for model
`sldvhighlight`	Highlight model using data from Simulink Design Verifier analysis
`sldvreport`	Generate Simulink Design Verifier report
`sldvsimdata`	得到仿真数据在数据集format
`sldvruntestopts`	Generate simulation or execution options for sldvruntest or sldvruncgvtest
`sldvruntest`	Simulate model by using input data
`sldvharnessopts`	Default options for sldvmakeharness
`sldvmakeharness`	Generate harness model
`sldvmergeharness`	Merge test cases and initializations into one harness model

Topics

Highlighted Results on the Model

Describes highlighting of analysis results on the model.

Simulink Design Verifier Reports

Describes the different parts of aSimulink Design Verifierreport.

Simulink Design Verifier Harness Models

Describes a basic harness model.

Simulink Design Verifier Data Files

Describes the contents of aSimulink Design Verifierdata file.

Simulink Design Verifier Log Files

Describes the analysis log files.

Design Verifier Pane: Results

Specify options that control howSimulink Design Verifierhandles the results that it generates.

Design Verifier Pane: Report

Specify options that control howSimulink Design Verifierreports its results.

Review Analysis Results

Review analysis results in theSimulink Design VerifierResults Summary window.

Export Test Cases to Simulink Test

Describes how to generate test cases inSimulink TestusingSimulink Design Verifieranalysis results, which can be generated by property proving, design error detection, and test case generation.

Featured Examples

Simulate Harness Model with Signal Editor Inputs Block

Generate model coverage report by simulating the test harness model with the Signal Editor Inputs block. You can simulate a single test case or counterexample by selecting the active scenario in the Signal Editor dialog box. For more information see, Simulate Harness Model by Using the Signal Editor Inputs Block.

Open Script

Results Interpretation and Use

Functions

Topics

Featured Examples

Simulate Harness Model with Signal Editor Inputs Block

Simulink Design Verifier Documentation

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