Decrease real-world value of signal by one - Simulink - 金宝app,下载188bet金宝搏,金宝搏官方网站

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Simulink / Additional Math & Discrete / Additional Math: Increment - Decrement
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Ports

Input

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`Port_1`— Input signal
scalar | vector | matrix

Input signal, specified as a scalar, vector, or matrix.

Output

expand all

`Port_1`— Output signal
scalar | vector | matrix

Output is the real-world value of the input signal decreased by one. Overflows always wrap. The output has the same data type and dimensions as the input.

Model Examples

Increment and Decrement Real-World Values

Increase and decrease the real-world value of a signal using the Increment Real World, Decrement Real World, Decrement Time To Zero, and Decrement To Zero blocks.

Open Model

Block Characteristics

Data Types	`double`\|`fixed point`\|`integer`\|`single`
Direct Feedthrough	`no`
Multidimensional Signals	`no`
Variable-Size Signals	`yes`
Zero-Crossing Detection	`no`

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

The code generator does not explicitly group primitive blocks that constitute a nonatomic masked subsystem block in the generated code. This flexibility allows for more efficient code generation. In certain cases, you can achieve grouping by configuring the masked subsystem block to execute as an atomic unit by selecting the治疗作为原子单元option.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is`0`. For more details, seeConstrainedOutputPipeline(HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is`0`. For more details, seeInputPipeline(HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is`0`. For more details, seeOutputPipeline(HDL Coder).

Decrement Real World

Description

Ports

Input

`Port_1`— Input signal
scalar | vector | matrix

Output

`Port_1`— Output signal
scalar | vector | matrix

Model Examples

Increment and Decrement Real-World Values

Block Characteristics

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

See Also

Topics

Decrement Real World

Description

Ports

Input

Port_1— Input signalscalar | vector | matrix

Output

Port_1— Output signalscalar | vector | matrix

Model Examples

Increment and Decrement Real-World Values

Block Characteristics

Extended Capabilities

C/C++ Code GenerationGenerate C and C++ code using Simulink® Coder™.

HDL Code GenerationGenerate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point ConversionDesign and simulate fixed-point systems using Fixed-Point Designer™.

Version History

See Also

Topics

`Port_1`— Input signal
scalar | vector | matrix

`Port_1`— Output signal
scalar | vector | matrix

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.