创建具有变化条件的公共汽车

This example shows how to create bus signals with elements having different variant conditions. This model has two signals (‘a’, ‘b’) that are merged to create a bus signal. These two signals have different variant conditions, V==1 and W == 1.

总线选择器由两个具有两个不同变体条件的信号（v == 1和w == 1）馈送。当此总线信号被馈入总线选择器时，当您从总线中选择各个信号时，也会选择变体条件。

To see the completed model, open theslexVariantBusmodel.

Variant Condition Propagation with Bus

AVariant Sourceblock can accept either virtual or nonvirtual bus inputs.

考虑这个模型。

Bus is created with variant conditions V = 1 and W = 1. When conditions V and W are propagated through the bus and when individual elements are selected from the bus, conditions are also selected.

Code Generation

您可以为模型生成代码。为此，Appstab of toolstrip, clickEmbedded Coder, then on theC代码tab, clickBuild. For more information on configuring model to generate code, see为代码生成准备含有变体的模型.

When generating code with preprocessor conditionals, the bus types and hierarchies of all bus inputs must be the same.

虚拟和Nonvirtual Bus Behavior

Virtual buses provide the simplest approach for using buses to reduce signal clutter in a block diagram. Nonvirtual buses support modeling components (such as S-functions orMATLAB Functionblocks) that require explicitly specified interfaces. There is no change in the propagation behavior of variant conditions when variant conditions are propagated through a virtual or nonvirtual bus.

为虚拟总线生成的代码如下所示。

/*Block states (default storage)forsystem''*/ typedefstruct{#ifV == 1 real_TUnitDelay_1_DSTATE;/*'/Unit Delay'*/ #define D_WORK_EX_BUS_VAR_COND_VARIANT_EXISTS #endif /* V == 1 */ #ifW == 1 int32_TUnitDelay_2_DSTATE;/*'/Unit Delay'*/ #define D_WORK_EX_BUS_VAR_COND_VARIANT_EXISTS #endif /* W == 1 */ #ifndef D_WORK_EX_BUS_VAR_COND_VARIANT_EXISTS char_rt_unused;#endif } D_Work_ex_bus_var_cond;

Code generated for a nonvirtual bus is as shown below.

/*Block states (default storage)forsystem''*/ typedefstruct{#ifV == 1 || W == 1 myBusunitdelay_dstate;/*'/Unit Delay'*/ #define D_WORK_EX_BUS_VAR_COND_VARIANT_EXISTS #endif /* V == 1 || W == 1 */ #ifndef D_WORK_EX_BUS_VAR_COND_VARIANT_EXISTS char_rt_unused;#endif } D_Work_ex_bus_var_cond;

You must have an associated bus object in the bus, which provides properties that Simulink^®uses to validate the bus signal. For more information on bus objects, seeSpecify Bus Properties with Simulink.Bus Object Data Types. The bus object used in the bus is unconditional and it generates unguarded code as shown below.

Typedefstruct{real_ta;int32_Tb;} myBus;

Variant Bus with Model Block

Consider this model containing aModelblock.

This model has two signals (‘a’, ‘b’) which have different variant conditions, V==1 and V==2.

From theModelblock, the bus selector is fed two signals having two different variant conditions (V==1 and V==2). When you select the individual signals from the bus, the variant conditions are also selected.

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