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Check for Specified Minimum and Maximum Value Violations

During a design error detection analysis, the software checks the specified minimum and maximum values on intermediate signals throughout the model and on the output ports. These values define thedesign ranges.

The analysis checks for specified minimum and maximum values on:

  • 金宝app®block outputs, with the exception of the limitations described in the next section

  • Simulink.Signalobjects

  • Stateflow®data objects

  • MATLAB®for code generation data objects

  • Global data store writes

If the analysis detects that a signal exceeds the design range, the results identify where in the model the errors occurred. In addition, you can generate a harness model that contains test cases that demonstrate how the error occurred.

检查指定最小和马克西的局限性mum Value Violations

If you analyze a model checking if specified minimum and maximum values are exceeded, the software cannot check minimum and maximum values specified on:

  • AnyMuxblock with an output connected to aSelectorblock

  • Mergeblock inputs

    To work around this limitation, use aSimulink.Signalobject on theMergeblock output and specify the range on theSimulink.Signalobject.

Note

For information about how aSimulink Design Verifier™analysis handles specified minimum and maximum values on input ports, seeMinimum and Maximum Input Constraints.

About This Example

In this section, you create and analyze a model that has specified design minimum and maximum values on:

  • The input ports

  • The output ports of two of the intermediate blocks

The design error detection analysis identifies blocks where the output values exceed the design range. If the analysis detects this error, this example demonstrates how the analysis uses the specified minimum and maximum values when continuing the analysis.

Create the Example Model

Create the model for this example:

  1. In theMATLABtoolstrip, on theHometab, selectNew>Simulink Model.

  2. From the Simulink Commonly Used Blocks library, add the following blocks to the model and assign the indicated parameter values.

    Block Tab Parameter Value
    Inport Signal Attributes Minimum 0
    Inport Signal Attributes Maximum 5
    Gain Main Gain 5
    Gain Signal Attributes 输出minimum 0
    Gain Signal Attributes 输出maximum 20
    Gain Signal Attributes 输出data type int16
    Saturation Main Upper limit 25
    Saturation Main Lower limit -25
    Saturation Signal Attributes 输出minimum -25
    Saturation Signal Attributes 输出maximum 25
    Outport No changes

  3. 连接如图所示的四块。

  4. To display the specified minimum and maximum values, on theDebugtab, selectInformation Overlays>Signal Data Ranges.

  5. On theModelingtab, clickModel Settings.

  6. In the Configuration Parameters dialog box, on theSolverpane, underSolver selection:

    1. SetTypetoFixed-step.

      TheSimulink Design Verifiersoftware does not support variable-step solvers.

    2. SetSolvertodiscrete (no continuous states).

  7. On theDesign Verifier窗格中,设置ModetoDesign error detection.

  8. On theDesign Verifier>Design Error Detectionpane:

    1. SelectSpecified minimum and maximum value violations.

    2. Clear theInteger overflowandDivision by zeroparameters.

    In this example, you check only for intermediate minimum and maximum violations.

  9. To save these settings and exit the Configuration Parameters dialog box, clickOK.

  10. Save the model and name itex_interim_minmax.

Analyze the Model

To analyze the example model to identify any intermediate signals that violate the specified minimum and maximum values, perform design error detection analysis.

On theDesign Verifiertab, clickDetect Design Errors.

After the analysis is complete:

  • The software highlights the model with the analysis results.

  • TheSimulink Design VerifierResults dialog box opens and displays a summary of the analysis.

Review the Analysis Results

Review Results on the Model

In the model window, theGainblock is colored red and theSaturationblock is colored green. This indicates that:

  • At least one objective associated with theGainblock was falsified. For this example, the analysis falsified exactly one objective.

  • All objectives associated with theSaturationblock were satisfied. For this example, the analysis satisfied exactly one objective.

To understand these results:

  1. Click theGainblock.

    TheSimulink Design VerifierResults window shows that the design range for the output was [0..20], but the analysis detected an error and generated a test case that demonstrates that error. Because the design range for the input block is [0..5], when the input to theGainblock is 5, the output is 25, which exceeds the specified maximum value on that port.

    The analysis computes and displays the derived range to help you understand how the design range was exceeded.

  2. Click theSaturationblock.

    TheSimulink Design VerifierResults window shows that the output of theSaturationblock never exceeded the design range [–25..25]. The input to theSaturationblock never exceeded [0..25], which is the derived range that the analysis propagated from theGainblock.

Review the Harness Model

When the analysis completes, you can create a harness model contains the test cases that result in errors.

For the example model, view the test case that caused the design range error in the Gain block:

  1. After the analysis completes and the model is highlighted, click the Gain block.

  2. In theSimulink Design VerifierResults window, clickView test case.

    The software creates a harness model namedex_interim_minmax_harnessand opens theSignal Builderblock in the harness model that contains the test case.

    In theSignal Builderblock, one test case, whose signal value is 5, caused the output of the Gain block to be 25, which exceeds the specified maximum of 20.

  3. Before you simulate this test case, in the Configuration Parameters dialog box, on theDiagnostics > Data Validity窗格中,设置Simulation range checkingtowarningorerror.

    Setting this parameter specifies the diagnostic action to take if Simulink detects signals that exceed specified minimum or maximum values during simulation.

    • If you specifywarning, the simulation displays a warning message and continues.

    • If you specifyerror, the simulation displays an error message and stops.

  4. ClickOKto save your change and close the Configuration Parameters dialog box.

  5. In theSignal Builderblock window, clickStart simulationto simulate the model with this test case.

    As expected, in the MATLAB window, the simulation displays a warning or error that the output value of the Gain block exceeds the specified maximum.

Review the Analysis Report

You can also generate an HTML report containing detailed information about the analysis report for theex_interim_minmaxmodel. To create this report, in theSimulink Design VerifierResults window, clickGenerate detailed analysis report. The analysis report opens in a browser.

In the analysis report, theDesign Error Detection Objectives Statuschapter of the report provides detailed results in two categories:

  • Objectives Proven Valid— The output values for theSaturationblock are always within the design range.

  • Objectives Falsified with Test Cases— The output values for theGainblock violated the design range.