Introduction

DDCs are widely used in digital communication receivers to convert radio frequency (RF) or intermediate frequency (IF) signals to baseband. The DDC operation shifts the signal to a lower frequency and reduces its sampling rate to facilitate subsequent processing stages. The DDC in this example performs complex frequency translation followed by sample rate conversion using a four-stage filter chain. The example starts by designing the DDC with DSP System Toolbox™ functions in floating point. Then, each stage is converted to fixed point, and used in a Simulink® model that generates synthesizable HDL code. The example uses these two test signals to demonstrate and verify the DDC operation:

该示例将浮点DDC输出的信号质量与定点DDC输出处的信号质量进行比较。

Finally, the example presents an implementation of the filter chain for FPGAs, and synthesis results.

此示例使用DDCTestUtils，一个辅助类，其中包含用于生成刺激和分析DDC输出的功能。有关更多信息，请参阅DDCTestUtils.mfile.

DDC Structure

The DDC consists of a numerically controlled oscillator (NCO), mixer, and decimating filter chain. The filter chain consists of a cascade integrator-comb (CIC) decimator, CIC gain correction, a CIC compensation decimator (FIR), a halfband FIR decimator, and a final FIR decimator.

过滤器链的总体响应等效于具有相同规范的单个拆卸滤波器。但是，将过滤器分为多个拆卸阶段会导致更有效的设计，该设计使用更少的硬件资源。

CIC清除仪提供了较大的初始分解因子，使后续过滤器能够以较低的速率工作。CIC补偿分解仪通过补偿CIC下垂，同时将两个响应提高了光谱响应。半带是一个中间摘要，最终的删除器实现了精确的FpassandFstopcharacteristics of the DDC. The lower sampling rates near the end of the chain mean the later filters can optimize resource use by sharing multipliers.

This figure shows a block diagram of the DDC.

The sample rate of the input to the DDC is 122.88 Msps, and the output sample rate is 1.92 Msps. These rates give an overall decimation factor of 64. LTE receivers use 1.92 Msps as the typical sampling rate for cell search and master information block (MIB) recovery. The DDC filters are designed to suit this application. The DDC is optimized to run at a clock rate of 122.88 MHz.

DDC Design

This section explains how to design the DDC using floating-point operations and filter-design functions in MATLAB®.

DDC Parameters

This example designs the DDC filter characteristics to meet these specifications for the given input sampling rate and carrier frequency.

FSIN = 122.88E6;% Sampling rate of DDC inputFsOut = 1.92e6;% Sampling rate of DDC outputFc = 32e6;% Carrier frequencyFpass = 540e3;% Passband frequency, equivalent to 36x15kHz LTE subcarriersFSTOP = 700E3;% Stopband frequencyAp = 0.1;% Passband rippleAST = 60;％停止带衰减

CIC Decimator

The first filter stage is a CIC decimator because of its ability to efficiently implement a large decimation factor. The response of a CIC filter is similar to a cascade of moving average filters, but a CIC filter uses no multiplication or division. As a result, the CIC filter has a large DC gain.

cicparams.decimationFactor = 8;cicparams.differentialdelay = 1;cicparams.numsections = 3;cicparams.fsout = fsin/cicparams.decimationFactor;cicfilt = dsp.cicdecectrator（cicparams.decimationfactor，...cicparams.differentialdelay，cicparams.numsections）％＃ok <*nopts>cicgain =增益（cicfilt）

cicFilt = dsp.CICDecimator with properties: DecimationFactor: 8 DifferentialDelay: 1 NumSections: 3 FixedPointDataType: 'Full precision' cicGain = 512

因为中投获得是2的幂,硬件implementation can easily correct for the gain factor by using a shift operation. For analysis purposes, the example represents the gain correction in MATLAB with a one-tapdsp.FIRFilterSystem object™.

cicGainCorr = dsp.FIRFilter('Numerator',1/cicGain)

cicGainCorr = dsp.FIRFilter with properties: Structure: 'Direct form' NumeratorSource: 'Property' Numerator: 0.0020 InitialConditions: 0 Use get to show all properties

Display the magnitude response of the CIC filter with and without gain correction by usingfvtool. For analysis, combine the CIC filter and the gain correction filter into adsp.FilterCascade系统对象。CIC过滤器在内部使用固定点算术，因此fvtoolplots both the quantized and unquantized responses.

ddcPlots.cicDecim = fvtool(...cicFilt,...dsp.FilterCascade(cicFilt,cicGainCorr),...'fs'，[fsin，fsin]）;传奇（ddcplots.cicdecim，...'CIC No Correction',...“ CIC具有增益校正”);

CIC Droop Compensation Filter

Because the magnitude response of the CIC filter has a significant下垂within the passband region, the example uses a FIR-based droop compensation filter to flatten the passband response. The droop compensator has the same properties as the CIC decimator. This filter implements decimation by a factor of two, so you must also specify bandlimiting characteristics for the filter. Use thedesignfunction to return a filter System object with the specified characteristics.

compParams.R = 2;％CIC补偿分解因子compParams.Fpass = Fstop;% CIC compensation passband frequencycompParams.FsOut = cicParams.FsOut/compParams.R;% New sampling ratecompParams.Fstop = compParams.FsOut - Fstop;% CIC compensation stopband frequencycompParams.Ap = Ap;% Same passband ripple as overall filtercompParams.Ast = Ast;% Same stopband attenuation as overall filtercompSpec = fdesign.decimator(compParams.R,'ciccomp',...cicParams.DifferentialDelay,...cicParams.NumSections,...cicParams.DecimationFactor,...'Fp,Fst,Ap,Ast',...compParams.Fpass,compParams.Fstop,compParams.Ap,compParams.Ast,...cicParams.FsOut); compFilt = design(compSpec,'SystemObject',true)

compFilt = dsp.FIRDecimator with properties: DecimationFactor: 2 NumeratorSource: 'Property' Numerator: [-0.0398 -0.0126 0.2901 0.5258 0.2901 -0.0126 -0.0398] Structure: 'Direct form' Use get to show all properties

Plot the combined response of the CIC filter (with gain correction) and droop compensation.

ddcPlots.cicComp = fvtool(...dsp.FilterCascade(cicFilt,cicGainCorr,compFilt),...'fs',FsIn,'Legend','off');

Halfband Decimator

The halfband filter provides efficient decimation by two. Halfband filters are efficient because approximately half of their coefficients are equal to zero, and those multipliers are excluded from the hardware implementation.

hbParams.FsOut = compParams.FsOut/2; hbParams.TransitionWidth = hbParams.FsOut - 2*Fstop; hbParams.StopbandAttenuation = Ast; hbSpec = fdesign.decimator(2,'halfband',...'Tw,Ast',...hbParams.TransitionWidth,...hbParams.StopbandAttenuation,...compParams.FsOut); hbFilt = design(hbSpec,'SystemObject',true)

hbFilt = dsp.FIRDecimator with properties: DecimationFactor: 2 NumeratorSource: 'Property' Numerator: [0.0089 0 -0.0565 0 0.2977 0.5000 0.2977 0 -0.0565 ... ] Structure: 'Direct form' Use get to show all properties

Plot the response of the DDC up to the halfband filter output.

ddcPlots.halfbandFIR = fvtool(...dsp.FilterCascade(cicFilt,cicGainCorr,compFilt,hbFilt),...'fs',FsIn,'Legend','off');

Final FIR Decimator

The final FIR implements the detailed passband and stopband characteristics of the DDC. This filter has more coefficients than the earlier FIR filters, but because it operates at a lower sampling rate it can use resource sharing for an efficient hardware implementation.

将3 dB的净空添加到停止带衰减中，以便DDC在定量量化后仍然符合规格。通过使用经验发现该值fvtool.

finalSpec = fdesign.decimator(2,'lowpass',...'Fp,Fst,Ap,Ast',Fpass,Fstop,Ap,Ast+3,hbParams.FsOut); finalFilt = design(finalSpec,'equiripple','SystemObject',true)

finalFilt = dsp.FIRDecimator with properties: DecimationFactor: 2 NumeratorSource: 'Property' Numerator: [9.3365e-04 0.0013 9.3466e-04 -5.3189e-04 -0.0022 ... ] Structure: 'Direct form' Use get to show all properties

Visualize the overall magnitude response of the DDC.

ddcfilterchain = dsp.filtercascade（cicfilt，cicgaincorr，compfilt，hbfilt，finalfilt）;ddcplots.overallresponse = fvtool（ddcfilterchain，'fs',FsIn,'Legend','off');

Fixed-Point Conversion

The frequency response of the floating-point DDC filter chain now meets the specification. Next, quantize each filter stage to use fixed-point types and analyze them to confirm that the filter chain still meets the specification.

Filter Quantization

此示例使用16-bit coefficients, which are sufficient to meet the specification. Using fewer than 18 bits for the coefficients minimizes the number of DSP blocks that are required for an FPGA implementation. The input to the DDC filter chain is 16-bit data with 15 fractional bits. The filter outputs are 18-bit values, which provide extra headroom and precision in the intermediate signals.

For the CIC decimator, choosing the“最小部分单词长度”fixed-point data type option automatically optimizes the internal wordlengths based on the output wordlength and other CIC parameters.

cicFilt.FixedPointDataType =“最小部分单词长度”;cicFilt.OutputWordLength = 18;

Configure the fixed-point properties of the gain correction and FIR-based System objects. The object uses the defaultRoundingMethodandOverflowActionproperty values ('Floor'and'裹'respectively).

% CIC Gain CorrectioncicGainCorr.FullPrecisionOverride = false; cicGainCorr.CoefficientsDataType ='Custom';cicGainCorr.CustomCoefficientsDataType = numerictype(fi(cicGainCorr.Numerator,1,16)); cicGainCorr.OutputDataType ='Custom';cicgaincorr.customoutputdatate = numerictype（1,18,16）;％CIC下垂补偿compFilt.FullPrecisionOverride = false; compFilt.CoefficientsDataType ='Custom';compfilt.customcoeffientsdatatepe = numerictype（[]，16,15）;compfilt.productdatate ='Full precision';compFilt.AccumulatorDataType ='Full precision';compfilt.outputDatatype ='Custom';compFilt.CustomOutputDataType = numerictype([],18,16);% HalfbandhbFilt.FullPrecisionOverride = false; hbFilt.CoefficientsDataType ='Custom';hbFilt.CustomCoefficientsDataType = numerictype([],16,15); hbFilt.ProductDataType ='Full precision';hbFilt.AccumulatorDataType ='Full precision';hbFilt.OutputDataType ='Custom';hbFilt.CustomOutputDataType = numerictype([],18,16);% FIRfinalFilt.fullPrecisionOverride = false;finalFilt.coefficientsDatatype ='Custom';finalFilt.customCoefficientsDatatepe = Numerictype（[]，16,15）;finalFilt.productDatatepe ='Full precision';finalFilt.AccumulatorDataType ='Full precision';finalFilt.OutputDataType ='Custom';finalFilt.CustomOutputDataType = numerictype([],18,16);

Fixed-Point Analysis

Inspect the quantization effects withfvtool. You can analyze the filters individually or in a cascade.fvtoolshows the quantized and unquantized (reference) responses overlayed. For example, this figure shows the effect of quantizing the final FIR filter stage.

ddcPlots.quantizedFIR = fvtool(finalFilt,...'fs'，hbparams.fsout，“算术”,'fixed');

重新定义ddcFilterChaincascade object to include the fixed-point properties of the individual filters. Then, usefvtoolto analyze the entire filter chain and confirm that the quantized DDC still meets the specification.

ddcFilterChain = dsp.FilterCascade(cicFilt,...cicGainCorr,compFilt,hbFilt,finalFilt); ddcPlots.quantizedDDCResponse = fvtool(ddcFilterChain,...'fs',FsIn,'Arithmetic','fixed'); legend(ddcPlots.quantizedDDCResponse,...'DDC filter chain');

HDL-Optimized Simulink Model

The next step in the design flow is to implement the DDC in Simulink using blocks that support HDL code generation.

Model Configuration

The model relies on variables in the MATLAB workspace to configure the blocks and settings. It uses the same filter chain variables defined earlier in the example. Next, define the NCO characteristics and the input signal. The example uses these characteristics to configure the NCO block.

指定所需的频率分辨率，并计算实现所需分辨率所需的累加器位数。设置所需的虚假自由动态范围，然后定义量化的累加器位的数量。NCO使用累加器的量化输出来解决正弦查找表。还要计算NCO用于生成指定载波频率的相位增量。NCO将相位抖动应用于量化过程中去除的那些累加器位。

nco.fd = 1;nco.accwl = nextPow2（fsin/nco.fd）+1;SFDR = 84;nco.quantaccwl = ceil（（SFDR-12）/6）;nco.phaseinc = round（（ -  fc*2^nco.accwl）/fsin）;nco.numditherbits = nco.accwl-nco.quantaccwl;

DDC的输入来自ddcInvariable. For now, assign a dummy value forddcInso that the model can compute its data types. During testing,ddcInprovides input data to the model.

ddcin = 0;%#ok

您可以通过设置基于示例的信号FrameSize至1，并在接收到每个样本时输出。对于更高的输入采样频率或降低功率的考虑，此设计还可以实现基于框架的处理，并且可以实现FrameSizeshould be modified accordingly. In this case, we're showing a case for theFrameSize4。

FrameSize = 4;

Model Structure

This figure shows the top level of the DDC Simulink model. The model imports theddcInvariable from the MATLAB workspace by using a Signal From Workspace block, converts the input signal to 16-bit values, and applies the signal to the DDC. You can generate HDL code from theHDL_DDCsubsystem.

modelName ='DDCforLTEHDL';open_system(modelName); set_param(modelName,“仿真”,'更新'); set_param(modelName,'Open','on');

TheHDL_DDC子系统实现了DDC过滤器。首先,数控O block generates a complex phasor at the carrier frequency. This signal goes to a mixer that multiplies the phasor with the input signal. Then, the output of the mixer is passed to the filter chain and decimated to 1.92 Msps.

set_param([modelName'/hdl_ddc'],'Open','on');

NCO块参数

The NCO block in the model is configured with the parameters defined in thencostructure. This figure shows both tabs of the NCO block parameters dialog.

CIC拆卸和获得校正

The first filter stage is a CIC Decimator that is implemented with a CIC Decimator block. The block parameters are set to thecicParamsstructure values. To implement the gain correction, the model selects theGain correctionparameter. The image shows the block parameters for the CIC Decimator block.

The model configures the filters by using the properties of the corresponding System objects. The CIC compensation, halfband decimation, and final decimation filters operate at effective sample rates that are lower than the clock rate by factors of 8, 16, and 32, respectively. The model implements these sample rates by using thevalid输入信号以指示哪些样品以每个速率有效。过滤器链中的信号都具有相同的Simulink样品时间。金宝app

CIC补偿，半带拆卸和最终拆卸过滤器均由FIR解剖器实施。通过设置有效输入之间的最小循环数参数，我们可以在输入样本之间使用无效的周期。例如，CIC补偿清除仪的每个输入之间的间距是8, which equals the decimation factor. So the CIC Compensation Decimator has the有效输入之间的最小循环数set toceil(cicParams.DecimationFactor/FrameSize), which equals2cycles. The image shows the block parameters for the CIC Compensation Decimation block.

The FIR Decimator block fully reuses the multipliers in time over the number of clock cycles you specify. ForFrameSizeis4，使用复杂输入数据的CIC补偿分解过滤器将使用4乘数。终于被赶下台Halfband使用4乘数和最终拆卸用途12乘数。ForFrameSizeis1, since the inputs spacing of CIC Compensation Decimation and Halfband Decimation are larger than their filter length, those two decimators only require2乘数。And the Final Decimation needs4multipliers at that time.

正弦波测试和验证

To test the DDC, modulate a 40 kHz sinusoid onto the carrier frequency and pass the modulated sine wave through the DDC. Then, measure the spurious- free dynamic range (SFDR) of the resulting tone and the SFDR of the NCO output. Plot the SFDR of the NCO and the fixed-point DDC output.

% Initialize random seed before executing any simulations.rng(0);% Generate a 40 kHz test tone, modulated onto the carrier.ddcIn = DDCTestUtils.GenerateTestTone(40e3,Fc);% Demodulate the test signal with the floating-point DDC.ddcOut = DDCTestUtils.DownConvert(ddcIn,FsIn,Fc,ddcFilterChain); release(ddcFilterChain);％通过运行Simulink模型来解码测试信号。金宝appout = sim(modelName);% Measure the SFDR of the NCO, floating-point DDC outputs, and fixed-point% DDC outputs.results.sfdrNCO = sfdr(real(out.ncoOut),FsIn); results.sfdrFloatDDC = sfdr(real(ddcOut),FsOut); results.sfdrFixedDDC = sfdr(real(out.ddcFixedOut),FsOut); disp('SFDR Measurements'); disp([' Floating-point DDC SFDR: ',num2str(results.sfdrFloatDDC)' dB'）;disp（[[“固定point NCO SFDR: '，num2str（results.sfdrnco）' dB'）;disp（[[' Optimized fixed-point DDC SFDR: ',num2str(results.sfdrFixedDDC)' dB'）;fprintf(newline);% Plot the SFDR of the NCO and fixed-point DDC outputs.ddcPlots.ncoOutSDFR = figure; sfdr(real(out.ncoOut),FsIn); ddcPlots.OptddcOutSFDR = figure; sfdr(real(out.ddcFixedOut),FsOut);

SFDR测量Floating-point DDC SFDR: 291.4184 dB Fixed-point NCO SFDR: 83.0306 dB Optimized fixed-point DDC SFDR: 110.386 dB

LTE Signal Test

You can use an LTE test signal to perform more rigorous testing of the DDC. Generate a standard-compliant LTE waveform by using LTE Toolbox™ functions. Then, downconvert the waveform with the DDC model. Use LTE Toolbox functions to measure the error vector magnitude (EVM) of the resulting signals.

rng(0);％仅在您拥有LTE工具箱产品时执行此测试。iflicense('测试','LTE_Toolbox')% Generate a modulated LTE test signal by using the LTE Toolbox functions.[ddcIn,sigInfo] = DDCTestUtils.GenerateLTETestSignal(Fc);% Downconvert the signal with the floating-point DDC.ddcOut = DDCTestUtils.DownConvert(ddcIn,FsIn,Fc,ddcFilterChain); release(ddcFilterChain);% Downconvert the signal with the Simulink model, then measure and plot the% EVM of the floating-point and fixed-point results. Pad the input with zeros% to represent propagation latency and return the complete result.ddcIn = [ddcIn;zeros(2480*FrameSize,1)]; out = sim(modelName); results.evmFloat = DDCTestUtils.MeasureEVM(sigInfo,ddcOut); results.evmFixed = DDCTestUtils.MeasureEVM(sigInfo,out.ddcFixedOut(1:length(ddcOut))); disp('LTE Error Vector Magnitude (EVM) Measurements'); disp([' Floating-point DDC RMS EVM: 'num2str(results.evmFloat.RMS*100,3)'％'）;disp（[[' Floating-point DDC Peak EVM: 'num2str(results.evmFloat.Peak*100,3)'％'）;disp（[[“固定point DDC RMS EVM: 'num2str（results.evmfixed.rms*100,3）'％'）;disp（[[“固定point DDC Peak EVM: 'num2str(results.evmFixed.Peak*100,3)'％'）;fprintf(newline);end

LTE误差矢量幅度（EVM）测量浮点DDC RMS EVM：0.633％浮点DDC峰EVM：2.44％固定点DDC RMS EVM：0.731％固定点DDC峰EVM：2.69％

HDL Code Generation and FPGA Implementation

要生成此示例的HDL代码，您必须具有HDL Coder™产品。使用makehdlandmakehdltb命令生成HDL代码和HDL测试工作台HDL_DDCsubsystem. The DDC was synthesized on a Xilinx® Zynq®-7000 ZC706 evaluation board. The table shows the post place-and-route resource utilization results. The design met timing with a clock frequency of 331 MHz.

T = table(...categorical({'LUT';'LUTRAM';'FF';'BRAM';'DSP'}）,...categorical({'4341';'383';'8248';'2.0';'36'}）,...'VariableNames',{'Resource','用法'}）

T = 5x2 table Resource Usage ________ _____ LUT 4341 LUTRAM 383 FF 8248 BRAM 2.0 DSP 36