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collectMemoryStatistics

Retrieve performance data from AXI interconnect monitor

Description

example

collectMemoryStatistics(profiler)retrieves performance data from theAXI interconnect monitorIP running on your hardware board. Theprofilerobject represents a connection to that IP. When theAXI interconnect monitoris configured in'Profile'mode, call this function in a loop to retrieve average transaction latency and counts of bursts and bytes while transactions are occurring. In'Trace'mode, call this function once after memory transactions are complete to retrieve detailed memory transaction event data.

Examples

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TheAXI interconnect monitor(目的)is an IP core that collects performance metrics for an AXI-based FPGA design. Create ansocIPCoreobject to setup and configure the AIM IP, and use thesocMemoryProfilerobject to retrieve and display the data.

For an example of how to configure and query the AIM IP in your design using MATLAB®as AXI Master, seeAnalyze Memory Bandwidth Using Traffic Generators. Specifically, review thesoc_memory_traffic_generator_axi_master.mscript that configures and monitors the design on the device.

The performance monitor can collect two types of data. ChooseProfilemode to collect average transaction latency and counts of bytes and bursts. In this mode, you can launch a performance plot tool, and then configure the tool to plot bandwidth, burst count, and transaction latency. ChooseTracemode to collect detailed memory transaction event data and view the data as waveforms.

Mode ='Profile';% or 'Trace'

To obtain diagnostic performance metrics from your generated FPGA design, you must set up a JTAG connection to the device from MATLAB. Load a.matfile that contains structures derived from the board configuration parameters. This file was generated by theSoC Buildertool. These structures describe the memory interconnect and masters configuration such as buffer sizes and addresses. Use thesocHardwareBoardobject to set up the JTAG connection.

load('soc_memory_traffic_generator_zc706_aximaster.mat'); hwObj = socHardwareBoard('Xilinx Zynq ZC706 evaluation kit','Connect',false); AXIMasterObj = socAXIMaster(hwObj);

Configure the AIM. ThesocIPCore对象提供了一个函数,执行initialization. Then, create ansocMemoryProfilerobject to gather the metrics.

apmCoreObj = socIPCore(AXIMasterObj,perf_mon,'PerformanceMonitor',“模式”,Mode); initialize(apmCoreObj); profilerObj = socMemoryProfiler(hwObj,apmCoreObj);

Retrieve performance metrics or signal data from a design running on the FPGA by using thesocMemoryProfilerobject functions.

For'Profile'mode, call thecollectMemoryStatisticsfunction in a loop.

NumRuns = 100;forn = 1:NumRuns collectMemoryStatistics(profilerObj);end
JTAG design setup time is long relative to FPGA transaction times, and if you have a small number of transactions in your design, they might have already completed by the time you query the monitor. In this case, the bandwidth plot shows only one sample, and the throughput calculation is not accurate. If this situation occurs, increase the total number of transactions the design executes.

For'Trace'mode, call thecollectMemoryStatisticsfunction once. This function stops the IP from writing transactions into the FIFO in theAXI interconnect monitorIP, although the transactions continue on the interconnect. Set the size of the transaction FIFO,Trace capture depth, in the configuration parameters of the model, underHardware Implementation>Target hardware resources>FPGA design (debug).

collectMemoryStatistics(profilerObj);

Visualize the performance data by using theplotMemoryStatisticsfunction. In'Profile'mode, this function launches a performance plot tool, and you can configure the tool to plot bandwidth, burst count, and average transaction latency. In'Trace'mode, this function opens theLogic Analyzertool to view burst transaction event data.

plotMemoryStatistics(profilerObj);

Input Arguments

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Memory profiler object, specified as ansocMemoryProfilerobject that provides access to theAXI memory interconnectIP running on the hardware board.

版本历史

Introduced in R2019a