RS Decoder

Decode and recover message from RS codeword

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Library:
Wireless HDL Toolbox / Error Detection and Correction

Description

TheRS Decoderblock decodes and recovers a message from a Reed-Solomon (RS) codeword. The block accepts codeword data and asamplecontrolbus and outputs a decoded message data, asamplecontrolbus, whether the received data is corrupted, a block ready indicator, and (optionally) the number of corrected errors. The block provides an architecture suitable for HDL code generation and hardware deployment and supports shortened message lengths.

Because, the latency of the block varies, the block provides output portnextFramethat indicates when the block is ready to accept new input codeword data. For more details about latency, see theAlgorithmssection.

You can use this block to model many communication system forward error correcting (FEC) codes. The block supports digital subscriber line (DSL), WiMAX (802.16 m and e), digital video broadcast handheld (DVB-H) terminals, digital video broadcast satellite (DVB-S) services, and digital video broadcast satellite services to handheld (DVB-SH) devices below 3 MHz.

Ports

Input

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`data`— Input codeword data
scalar

Input codeword data, specified as a scalar representing one symbol.

The length of the codeword in symbols specified by theCodeword length (N)parameter must be an integer equal to 2^M– 1, whereMis an integer in the range from 3 to 16.

The input data word length must be an unsigned integer equal toceil(log₂(Codeword length (N))). For a codeword length of7, the input data word length must be 3.

doubleandsingledata types are allowed for simulation, but not for HDL code generation.

Data Types:double|single|uint8|uint16|fixed point

`ctrl`— Control signals accompanying sample stream
`samplecontrol`bus

Control signals accompanying the sample stream, specified as asamplecontrolbus. The bus includes thestart,end, andvalidcontrol signals, which indicate the boundaries of the frame and the validity of the samples.

start— Indicates the start of the input frame
end— Indicates the end of the input frame
valid— Indicates that the data on the inputdataport is valid

For more details, seeSample Control Bus.

Data Types:bus

Output

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`data`— Decoded message data
scalar

Decoded message data, returned as a scalar. This output data width is the same as the input data width.

Data Types:double|single|uint8|uint16|fixed point

`ctrl`— Control signals accompanying sample stream
`samplecontrol`bus

Control signals accompanying the sample stream, returned as asamplecontrolbus. The bus includes thestart,end, andvalidcontrol signals, which indicate the boundaries of the frame and the validity of the samples.

start— Indicates the start of the output frame
end— Indicates the end of the output frame
valid— Indicates that the data on the outputdataport is valid

For more details, seeSample Control Bus.

Data Types:bus

`err`— Indication of corruption of received data
scalar

Indication of corruption of the received data, returned as a scalar.

When this value is1(true), the output contains errors. When this value is0(false), the output contains zero errors.

If the number of errors in the input codeword is greater than (Codeword length (N)–Message length (K))/2, the block outputs data without correcting the errors and sets theerrport to1(true) to indicate that errors that cannot be corrected exist in the input codeword.

Data Types:Boolean

`nextFrame`— Block ready indicator
scalar

Block ready indicator, returned as a scalar.

The block sets this signal to1(true) when the block is ready to accept the start of the next frame. If the block receives an inputctrl.startsignal whilenextFrameis0(false), the block discards the frame in progress and begins processing the new data.

Data Types:Boolean

`numErrors`— Number of corrected errors
nonnegative scalar

Number of corrected errors, returned as a nonnegative scalar.

The maximum number of errors an RS code can correct is equal to (Codeword length (N)–Message length (K))/2. If the number of errors in the input codeword is greater than (Codeword length (N)–Message length (K))/2, the block outputs data without correcting the errors and sets thenumErrorsport to0to indicate that none of those errors can be corrected.

Dependencies

To enable this port, select theOutput number of corrected symbol errorsparameter.

Data Types:uint8

Parameters

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`Codeword length (N)`— Length of codeword
`7`(default) | range from 7 to 65,535

Specify the codeword length.

The codeword lengthNmust be an integer equal to 2^M– 1, whereMis an integer in the range from 3 to 16. For more information on representing data for RS codes, seeInteger Format (Reed-Solomon Only).

`Message length (K)`— Length of message
`3`(default) | integer in the range from 3 to (Codeword length (N)–`2`)

Specify the message length.

For more information on representing data for RS codes, seeInteger Format (Reed-Solomon Only).

`Source of primitive polynomial`— Primitive polynomial source
`Auto`(default) |`Property`

Specify the source of the primitive polynomial.

SelectAutoto specify the primitive polynomial based on theCodeword length (N)parameter value. The degree of the primitive polynomial is calculated asM=ceil(log₂(Codeword length (N))).
SelectPropertyto specify the primitive polynomial using thePrimitive polynomialparameter.

`Primitive polynomial`— Primitive polynomial
`[1 0 1 1]`(default) | binary row vector

Specify a binary row vector representing the primitive polynomial in descending order of powers.

For more information on how to specify a primitive polynomial, seePrimitive Polynomials and Element Representations.

Dependencies

To enable this parameter, set theSource of primitive polynomialparameter toProperty.

`Source of B, the starting power for roots of the primitive polynomial`— Source of starting power for roots of primitive polynomial
`Auto`(default) |`Property`

Specify the source of the starting power for roots of the primitive polynomial.

SelectAuto, to use the defaultB valueparameter value,1.
SelectProperty要启用B valueparameter.

`B value`— Starting power of roots
`1`(default) | positive integer

Specify the starting power for roots of the primitive polynomial.

Dependencies

To enable this parameter, set theSource of B, the starting power for roots of the primitive polynomialparameter toProperty.

`Output number of corrected symbol errors`— Number of corrected symbol errors
`off`(default) |`on`

Select this parameter to enable thenumErrorsoutput port. This port outputs the number of corrected errors.

Model Examples

Decode and recover message from RS codeword

Use RS Decoder block to decode and recover a message from a Reed-Solomon (RS) codeword. In this example, a set of random inputs are generated and provided to thecomm.RSEncoderfunction and its output is provided to the RS Decoder block. The output of the RS Decoder block is compared with the input of thecomm.RSEncoderfunction to check whether any errors are encountered. The example model supports HDL code generation for theRS Decodersubsystem.

Open Script

Algorithms

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这图显示了不同的业务阶段ns performed by theRS Decoderblock. The block calculates syndrome values, determines the error location polynomial using Berlekamp-Massey algorithm, finds error locations and magnitudes using Chien search[5]and Forney[6]algorithms, respectively, and corrects the errors. For information about Berlekamp-Massey algorithm, seeAlgorithms for BCH and RS Errors-only Decoding.

Latency

有效的输入数据和收款银行之间的延迟sponding valid output data depends on the length of the codeword and the time the block takes to calculate error locating polynomials and find error locations and magnitudes. The time for which thenextFrameport value remains0depends on the processing time of the block. The processing time of the block is equal to the sum of the time the block takes to compute error locating polynomial (ELPTime) and find error locations and error magnitudes (ConvTime). The processing time is calculated as this value.

$\begin{array}{l} P r o c e s s i n g_t i m e = E L P T i m e + C o n v T i m e \\ = 4 \times t + t (2 \times t + 1) + 10 (P i p e l i n i n g d e l a y s) \end{array}$

tis the number of errors an RS code can correct and is equal to (Codeword length (N)–Message length (K))/2.

The latency of the block is 2^{ceil (log₂Processing_time)}+ 2 xCodeword length (N)+ 2.

This figure shows a sample output of theRS Decoderblock with latency according to the DVB-S standard configuration, andCodeword length (N)andMessage length (K)parameter values specified as255and239, respectively. In this case, when the processing time is less than theCodeword length (N), the block provides support for a continuous input. The latency of the block is 769 clock cycles.

Performance

The performance of the synthesized HDL code varies with your target and synthesis options. The input data type used for generating HDL code isfixdt(0,8,0).

This table shows the resource and performance data synthesis results when using the block withCodeword length (N)andMessage length (K)parameter values specified as255and239, respectively. The generated HDL is targeted to the Xilinx^®Zynq^®- 7000 ZC706 evaluation board. The design achieves a clock frequency of 161.5 MHz.

Resource	Number Used
LUTs	4098
Registers	2756
DSPs	0
Block RAMs	20

References

[1] Wicker, Stephen B.Error Control Systems for Digital Communication and Storage. Englewood Cliffs, NJ: Prentice Hall, 1995.

[2] Berlekamp, Elwyn R.Algebraic Coding Theory. Revised edition. McGraw-Hill Series in Systems Science. New Jersey: World Scientific, 2015.

[3] Clark, George C., and J. Bibb Cain.Error-Correction Coding for Digital Communications. Applications of Communications Theory. New York: Plenum Press, 1981.

[4] Moon, Todd K.Chapter 6, Error Correction Coding: Mathematical Methods and Algorithms. Hoboken, N.J: Wiley-Interscience, 2005.

[5] Chien, R. “Cyclic Decoding Procedures for Bose- Chaudhuri-Hocquenghem Codes.”IEEE Transactions on Information Theory10, no. 4 (October 1964): 357–63.https://doi.org/10.1109/TIT.1964.1053699.

[6] Forney, G. “On Decoding BCH Codes.”IEEE Transactions on Information Theory11, no. 4 (October 1965): 549–57.https://doi.org/10.1109/TIT.1965.1053825.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink^®accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is`0`. For more details, seeConstrainedOutputPipeline(HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is`0`. For more details, seeInputPipeline(HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is`0`. For more details, seeOutputPipeline(HDL Coder).

Restrictions

You cannot generate HDL for this block inside aResettable Synchronous Subsystem(HDL Coder).

Version History

Introduced in R2020a

RS Decoder

Description