Video and Webinar Series

视觉处理FPGA

This series of videos will show you how to adapt your image and video processing algorithms to target an FPGA using a lane detection system as an example. Learn about the techniques used by our leading customers:

  • Adapting frame-based algorithms to operate on a stream of bits
  • A workflow to verify a streaming hardware implementation against a frame-based algorithm
  • Specific techniques used in the Vision HDL Toolbox™ lane detection example
  • Targeting the FPGA fabric of a System-on-Chip (SoC) device

5:15

Part 1: Vision Processing FPGA and ASIC Hardware ConsiderationsLearn about some of the key factors to consider when targeting a vision processing algorithm to FPGA or ASIC hardware.

5:07

Part 2: Workflow from a Frame-Based Algorithm to a Pixel-Streaming ImplementationReuse MATLAB vision processing scripts and algorithms to verify a Simulink hardware implementation.

5:22

Part 3: Hardware Design of a Lane Detection AlgorithmLearn about the hardware implementation techniques used in the Vision HDL Toolbox lane detection example.

4:58

Part 4: Targeting a Lane Detection Design to a Xilinx Zynq DeviceGenerate optimized fixed-point HDL to target the lane detection example to FPGA fabric.

4:58

Part 5: Hardware-Software Prototyping of a Lane Detection DesignPrototype a hardware-software implementation of an automated driving application using the Computer Vision Toolbox Support Package for Xilinx Zynq-Based Hardware.

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