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FPGA Board Customization

功能描述

Both HDL Coder™ and HDL Verifier™ software include a set of predefined FPGA boards you can use with the Turnkey or FPGA-in-the-loop (FIL) workflows. You can view the lists of these supported boards in the HDL Workflow Advisor or in the FIL wizard. With the FPGA Board Manager, you can add additional boards to use either of these workflows. To add a board, you need the relevant information from the board specification documentation.

The FPGA Board Manager is the hub for accessing wizards and dialog boxes that take you through the steps necessary to create a custom board configuration. You can also access options for:

Importing a custom board
复制板定义文件以进行进一步修改
Verifying a new board

Custom Board Management

您通过以下用户界面管理FPGA自定义板：

FPGA Board Manager：添加，导入，删除或以其他方式管理董事会定义文件的门户。
新的FPGA董事会向导：此向导可以通过创建一个自定义板定义文件，其中包括您从董事会规范文档中获得的信息。
FPGA董事会编辑: user interface for viewing or editing board information.

要开始，请审查FPGA董事会要求and then follow the steps described in创建自定义FPGA板定义。

FPGA董事会要求

FPGA Device

Select one of the following links to view a current list of supported FPGA device families:

For use with FPGA-in-the-loop (FIL), see金宝app支持FPGA Device Families for Board Customization。
要与FPGA交钥匙一起使用，请参阅金宝app支持FPGA Device Families for Board Customization（HDL编码器）。

FPGA Design Software

Altera^®Quartus^®II或Xilinx^®ISE is required. See product documentation for HDL Coder or HDL Verifier for the specific software versions required.

以下数学工作^®tools are required to use FIL or FPGA Turnkey.

工作流程	必需的工具
FPGA在环	HDL验证者定点Designer™
FPGA交钥匙	HDL Coder 金宝app^® Fixed-Point Designer

一般硬件要求

要使用FPGA开发委员会，请确保您拥有以下FPGA资源：

钟：需要连接到FPGA的外时钟。时钟可以是微分或单端。接受的时钟频率从5 MHz到300 MHz。与FIL一起使用时，时钟频率还有其他要求（请参阅FPGA-IN-IN-IN-IN-IN-IN-ENENENT连接要求).
Reset: An external reset signal connected to the FPGA is optional. When supplied, this signal functions as the global reset to the FPGA design.
JTAG下载电缆：FPGA编程需要连接主机计算机和FPGA板的JTAG下载电缆。FPGA必须使用Xilinx Impact或Altera Quartus II进行编程。

FPGA-IN-IN-IN-IN-IN-IN-ENENENT连接要求

金宝app支持的以太网PHY设备。在FPGA板上，以太网Mac在FPGA中实现。需要在FPGA板上进行以太网PHY芯片，以将物理介质连接到FPGA中的媒体访问（MAC）层。

笔记

When programming the FPGA, HDL Verifier assumes that there is only one download cable connected to the Host computer. It also assumes that the FPGA programming software automatically recognizes the cable. If not, use FPGA programming software to program your FPGA with the correct options.

The FIL feature is tested with the following Ethernet PHY chips and may not work with other Ethernet PHY devices.

以太网Phy芯片	测试
Marvell^®Alaska 88E1111	对于GMII，RGMII，SGMII和100个基本-T MII接口
国家半导体DP83848C	For 100 Base-T MII interface only

以太网PHY界面。The Ethernet PHY chip must be connected to the FPGA using one of the following interfaces:

界面	笔记
Gigabit Media Independent Interface (GMII)	Only 1000 Mbits/s speed is supported using this interface.
Reduced Gigabit Media Independent Interface (RGMII)	Only 1000 Mbits/s speed is supported using this interface.
Serial Gigabit Media Independent Interface (SGMII)	Only 1000 Mbits/s speed is supported using this interface.
媒体独立界面（MII）	使用此接口仅支持100 mbits/s速度。金宝app

笔记

对于GMII，不需要TXCLK（10/100 mbits信号的时钟信号）信号，因为仅支持1000 mbits/s速度。金宝app

In addition to the standard GMII/RGMII/SGMII/MII interface signals, FPGA-in-the-loop also requires an Ethernet PHY chip reset signal (ETH_RESET_n). This active-low reset signal performs the PHY hardware reset by FPGA. It is active-low.

Special Timing Considerations for RGMII.当使用RGMII接口时，FPGA上的MAC假设数据与原始RGMII V1.3标准中指定的参考时钟边缘对齐。在这种情况下，PC板设计为时钟信号提供了其他痕量延迟。

The RGMII v2.0 standard allows the transmitter to integrate this delay so that PC board delay is not required. Marvell Alaska 88E1111 has internal registers to add internal delays to RX and TX clocks. The internal delays are not added by default, which means that you must use the MDIO module to configure Marvell 88E1111 to add internal delays. For more information on the MDIO module, seeFIL I/O。

GMII/RGMII/SGMII接口的特殊时钟频率要求。当使用GMII/RGMII/SGMII接口时，FPGA需要精确的125 MHz时钟才能驱动1000 MBITS/S通信。该时钟是从用户使用时钟模块或PLL提供的外部时钟得出的。

并非所有外部时钟频率都可以得出精确的125 MHz时钟频率。可接受的时钟频率因FPGA设备系列而异。推荐的时钟频率为50、100、125和200 MHz。

JTAG Connection Requirements for FPGA-in-the-Loop

Vendor	Required Hardware	必需的软件
英特尔^®	USB Blaster I或USB Blaster II下载电缆	USB Blaster I或II驱动程序 For Windows^®操作系统：Quartus Prime可执行目录必须在系统路径上。对于Linux^®操作系统：不支持第四节以下的版本II 13.1。金宝app不支持Quartus II 14.1。金宝app仅支持64位Quartus。金宝appQuartus Library目录必须打开`ld_library_path`beforestarting MATLAB^®。预先在linux发行库路径上进行预先库之前的linux分发库路径`ld_library_path`。例如，`/lib/x86_64-linux-gnu：$ quartus_path`。
xilinx	数字^®下载电缆 If your board has an onboard Digilent USB-JTAG module, use a USB cable 如果您的板具有标准的Xilinx 14针JTAG连接器，请与Digilent的HS2或HS3电缆一起使用	For Windows operating systems: Xilinx Vivado^®executable directory must be on system path. 对于Linuxoperating systems: Digilent Adept 2. For the installation steps, seeInstall Digilent Adept 2 Runtime（Xilinx FPGA板的金宝appHDL验证支持包）。
xilinx	FTDI USB-JTAG cable 金宝app支持板上FT4232H，FT232H或FT2232H设备实现USB到JTAG的董事会支持	安装这些D2XX驱动程序。对于Windows操作系统：2.12.28（64位）对于Linuxoperating systems: 1.4.22 (64 bit) For the installation guide, seeD2XX驱动程序from the FTDI Chip website.
Microsemi^®	JTAG连接不支持金宝app