%导出工作流配置脚本百分比与MATLAB 9.5（R2018B PRERELEASE）于2018年29日14:42:37生成%该脚本使用以下参数值生成:% Filename: 'S:\generic_workflow_example.m'%覆盖:true%评论:正确% Headers: true% DUT: 'sfir_fixed/symmetric_fir'%需要查看修改后的工作流程，执行如下命令:％>> hwc.export（'dut'，'sfir_fixed / symmetric_fir'）;%--------------------------------------------------------------------------%%加载模型load_system (“sfir_fixed”）;%%将模型恢复为默认的HDL参数% hdlrestoreparams (' sfir_fixed / symmetric_fir ');%%模型HDL参数%%设置模型“sfir_fixed”HDL参数hdlset_param (“sfir_fixed”，“GenerateCoSimModel”，“ModelSim”）;hdlset_param (“sfir_fixed”，“GenerateHDLTestBench”，'离开'）;hdlset_param (“sfir_fixed”，“HDLSubsystem”，'sfir_fixed / symmetric_fir'）;hdlset_param (“sfir_fixed”，“SynthesisTool”，“Xilinx Vivado”）;hdlset_param (“sfir_fixed”，“SynthesisToolChipFamily”，“Virtex7”）;hdlset_param (“sfir_fixed”，“SynthesisToolDeviceName”，'xc7vx485t'）;hdlset_param (“sfir_fixed”，“SynthesisToolPackageName”，“ffg1761”）;hdlset_param (“sfir_fixed”，“SynthesisToolSpeedValue”，' 2 '）;hdlset_param (“sfir_fixed”，“TargetDirectory”，“hdl_prj \ hdlsrc”）;%%工作流配置设置使用默认设置构造工作流配置对象中国= hdlcoder。WorkflowConfig (“SynthesisTool”，“Xilinx Vivado”，“TargetWorkflow”，'通用ASIC / FPGA'）;%指定顶级项目目录中国。ProjectFolder =“hdl_prj”；%设置与合成工具版本相关的属性中国。所有owUnsupportedToolVersion = true;%设置要运行的工作流任务中国。RunTaskGenerateRTLCodeAndTestbench = true;中国。RunTaskVerifyWithHDLCosimulation = true;中国。RunTaskCreateProject = true;中国。RunTaskRunSynthesis = true;中国。RunTaskRunImplementation = false; hWC.RunTaskAnnotateModelWithSynthesisResult = true;%设置与RunTaskGenerateRTLCodeAndTestbench任务相关的属性hwc.generatertlcode = true;hwc.generatettestbench = false;hwc.genereValidationModel = false;设置与RunTaskCreateProject任务相关的属性中国。目标= hdlcoder.Objective.None;中国。AdditionalProjectCreationTclFiles ='＇；%设置与RunTaskRunSynthesis任务相关的属性中国。SkipPreRouteTimingAnalysis = false;％设置与“RunTaskRunimplingation”任务相关的属性hwc.ignoreplaceandrouteErrors = false;%设置与“RunTaskAnnotateModelWithSynthesisResult”任务相关的属性中国。CriticalPathSource =“pre-route”；中国。CriticalPathNumber = 1;中国。ShowAllPaths = false;中国。ShowDelayData = true;中国。ShowUniquePaths = false;中国。ShowEndsOnly = false;%验证工作流配置对象hWC.validate;%%运行工作流hdlcoder.runWorkflow ('sfir_fixed / symmetric_fir'、中国);

generic_workflow_example.m

%--------------------------------------------------------------------------％HDL工作流脚本%生成与MATLAB 9.5 (R2018b预发布)在15:11:23 on 04/05/2018%该脚本使用以下参数值生成:％filename：'c：\ users \ ggnanase \ desktop \ r2018b \ 18b_models \ ipcore_timing_failure \ hdlworkflow_fil.m'%覆盖:true%评论:正确% Headers: true% DUT: 'sfir_fixed/symmetric_fir'%需要查看修改后的工作流程，执行如下命令:％>> hwc.export（'dut'，'sfir_fixed / symmetric_fir'）;%--------------------------------------------------------------------------%%加载模型load_system (“sfir_fixed”）;%%将模型恢复为默认的HDL参数% hdlrestoreparams (' sfir_fixed / symmetric_fir ');%%模型HDL参数%%设置模型“sfir_fixed”HDL参数hdlset_param (“sfir_fixed”，“HDLSubsystem”，'sfir_fixed / symmetric_fir'）;hdlset_param (“sfir_fixed”，“SynthesisTool”，“Xilinx Vivado”）;hdlset_param (“sfir_fixed”，“SynthesisToolChipFamily”，“Kintex7”）;hdlset_param (“sfir_fixed”，“SynthesisToolDeviceName”，“xc7k325t”）;hdlset_param (“sfir_fixed”，“SynthesisToolPackageName”，“ffg900”）;hdlset_param (“sfir_fixed”，“SynthesisToolSpeedValue”，' 2 '）;hdlset_param (“sfir_fixed”，“TargetDirectory”，“hdl_prj \ hdlsrc”）;hdlset_param (“sfir_fixed”，“TargetFrequency”25);hdlset_param (“sfir_fixed”，“TargetPlatform”，'Xilinx Kintex-7 KC705开发板'）;hdlset_param (“sfir_fixed”，“工作流程”，“FPGA-in-the-Loop”）;%%工作流配置设置使用默认设置构造工作流配置对象中国= hdlcoder。WorkflowConfig (“SynthesisTool”，“Xilinx Vivado”，“TargetWorkflow”，“FPGA-in-the-Loop”）;%指定顶级项目目录中国。ProjectFolder =“hdl_prj”；%设置与合成工具版本相关的属性中国。所有owUnsupportedToolVersion = true;%设置要运行的工作流任务中国。RunTaskGenerateRTLCodeAndTestbench = true;中国。RunTaskVerifyWithHDLCosimulation = false;中国。RunTaskBuildFPGAInTheLoop = true;%设置与RunTaskGenerateRTLCodeAndTestbench任务相关的属性hwc.generatertlcode = true;hwc.generatettestbench = false;hwc.genereValidationModel = false;%设置与RunTaskBuildFPGAInTheLoop任务相关的属性中国。IPAddress =期间的“192.168.0.2；中国。MACAddress =“00-0A-35-02-21-8A”；中国。源文件='＇；中国。连接=“以太网”；hwc.runexternalbuild = true;%验证工作流配置对象hWC.validate;%%运行工作流hdlcoder.runWorkflow ('sfir_fixed / symmetric_fir'、中国);hdlcoder.runWorkflow (“hdlcoderUARTServoControllerExample / UART_Servo_on_FPGA”、中国);

fil_workflow_example.m.

%导出工作流配置脚本%生成的MATLAB 8.6 (R2015b)在14:24:32在08/07/2015％参数值：％filename：'s：\ turnkey_workflow_example.m'%覆盖:true%评论:正确% Headers: true％dut：'hdlcoderuartservocontrolleerxample / uart_servo_on_fpga'%%加载模型load_system ('hdlcoderuartservocontrollerexample'）;%%模型HDL参数%设置模型HDL参数hdlset_param ('hdlcoderuartservocontrollerexample'，．..“HDLSubsystem”，“hdlcoderUARTServoControllerExample / UART_Servo_on_FPGA”）;hdlset_param ('hdlcoderuartservocontrollerexample'，．..“SynthesisTool”，“Xilinx ISE”）;hdlset_param ('hdlcoderuartservocontrollerexample'，．..“SynthesisToolChipFamily”，“Virtex5”）;hdlset_param ('hdlcoderuartservocontrollerexample'，．..“SynthesisToolDeviceName”，“xc5vsx50t”）;hdlset_param ('hdlcoderuartservocontrollerexample'，．..“SynthesisToolPackageName”，'ff1136'）;hdlset_param ('hdlcoderuartservocontrollerexample'，．..“SynthesisToolSpeedValue”，' 1 '）;hdlset_param ('hdlcoderuartservocontrollerexample'，．..“TargetDirectory”，“hdl_prj \ hdlsrc”）;hdlset_param ('hdlcoderuartservocontrollerexample'，．..“TargetPlatform”，'Xilinx Virtex-5 ML506开发板'）;hdlset_param ('hdlcoderuartservocontrollerexample'，“工作流程”，'FPGA交钥匙'）;%设置导入HDL参数hdlset_param (“hdlcoderUARTServoControllerExample / UART_Servo_on_FPGA / uart_rxd”，．..“IOInterface”，'RS-232串行端口Rx'）;hdlset_param (“hdlcoderUARTServoControllerExample / UART_Servo_on_FPGA / uart_rxd”，．..“IOInterfaceMapping”，“[0]”）;%设置Outport HDL参数hdlset_param ('hdlcoderuartservocontrolleerexample / uart_servo_on_fpga / uart_txd'，．..“IOInterface”，RS-232串行端口Tx）;hdlset_param ('hdlcoderuartservocontrolleerexample / uart_servo_on_fpga / uart_txd'，．..“IOInterfaceMapping”，“[0]”）;%设置Outport HDL参数hdlset_param (“hdlcoderUARTServoControllerExample / UART_Servo_on_FPGA /版本”，．..“IOInterface”，' led General Purpose [0:7]'）;hdlset_param (“hdlcoderUARTServoControllerExample / UART_Servo_on_FPGA /版本”，．..“IOInterfaceMapping”，'[0：3]'）;%设置Outport HDL参数hdlset_param (“hdlcoderUARTServoControllerExample / UART_Servo_on_FPGA / pwm_output”，．..“IOInterface”，'膨胀头J6 Pin 2-64 [0:31]'）;hdlset_param (“hdlcoderUARTServoControllerExample / UART_Servo_on_FPGA / pwm_output”，．..“IOInterfaceMapping”，“[0]”）;%设置Outport HDL参数hdlset_param (“hdlcoderUARTServoControllerExample / UART_Servo_on_FPGA / servo_debug1”，．..“IOInterface”，'膨胀头J6 Pin 2-64 [0:31]'）;hdlset_param (“hdlcoderUARTServoControllerExample / UART_Servo_on_FPGA / servo_debug1”，．..“IOInterfaceMapping”，“[1]”）;%设置Outport HDL参数hdlset_param (“hdlcoderUARTServoControllerExample / UART_Servo_on_FPGA / servo_debug2”，．..“IOInterface”，'膨胀头J6 Pin 2-64 [0:31]'）;hdlset_param (“hdlcoderUARTServoControllerExample / UART_Servo_on_FPGA / servo_debug2”，．..“IOInterfaceMapping”，“[2]”）;%%工作流配置设置使用默认设置构造工作流配置对象中国= hdlcoder。WorkflowConfig (“SynthesisTool”，“Xilinx ISE”，．..“TargetWorkflow”，'FPGA交钥匙'）;%指定顶级项目目录中国。ProjectFolder =“hdl_prj”；%设置与合成工具版本相关的属性中国。所有owUnsupportedToolVersion = true;%设置要运行的工作流任务中国。RunTaskGenerateRTLCodeAndTestbench = true;中国。RunTaskVerifyWithHDLCosimulation = true;中国。RunTaskCreateProject = true;中国。RunTaskPerformLogicSynthesis = true;中国。RunTaskPerformMapping = true; hWC.RunTaskPerformPlaceAndRoute = true; hWC.RunTaskGenerateProgrammingFile = true; hWC.RunTaskProgramTargetDevice = false;%设置“创建项目任务”相关的属性中国。目标= hdlcoder.Objective.None;中国。AdditionalProjectCreationTclFiles ='＇；%设置“执行映射任务”相关属性中国。SkipPreRouteTimingAnalysis = true;%设置“执行地点和路由任务”的相关属性hwc.ignoreplaceandrouteErrors = false;%验证工作流配置对象hWC.validate;%%运行工作流hdlcoder.runWorkflow (“hdlcoderUARTServoControllerExample / UART_Servo_on_FPGA”、中国);

turnkey_workflow_example.m

%导出工作流配置脚本%生成的MATLAB 8.6 (R2015b)在14:42:16在08/07/2015％参数值：% Filename: 'S:\ip_core_gen_workflow_example.m'%覆盖:true%评论:正确% Headers: true% DUT: 'hdlcoder_led_blink /led_counter'%%加载模型load_system (“hdlcoder_led_blinking”）;%%模型HDL参数%设置模型HDL参数hdlset_param (“hdlcoder_led_blinking”，．..“HDLSubsystem”，“hdlcoder_led_blinking / led_counter”）;hdlset_param (“hdlcoder_led_blinking”，'OptimizationReport'，“上”）;hdlset_param (“hdlcoder_led_blinking”，．..“ReferenceDesign”，'默认系统(Qsys 14.0)'）;hdlset_param (“hdlcoder_led_blinking”，“ResetType”，“同步”）;hdlset_param (“hdlcoder_led_blinking”，“ResourceReport”，“上”）;hdlset_param (“hdlcoder_led_blinking”，“SynthesisTool”，“阿尔特拉第四的二世”）;hdlset_param (“hdlcoder_led_blinking”，“SynthesisToolChipFamily”，“气旋V”）;hdlset_param (“hdlcoder_led_blinking”，“SynthesisToolDeviceName”，“5 csxfc6d6f31c6”）;hdlset_param (“hdlcoder_led_blinking”，“TargetDirectory”，“hdl_prj \ hdlsrc”）;hdlset_param (“hdlcoder_led_blinking”，．..“TargetPlatform”，Altera Cyclone V SoC development kit - Rev.D）;hdlset_param (“hdlcoder_led_blinking”，“可追溯性”，“上”）;hdlset_param (“hdlcoder_led_blinking”，“工作流程”，'IP核心生成'）;%设置子系统HDL参数hdlset_param (“hdlcoder_led_blinking / led_counter”，．..“ProcessorFPGASynchronization”，“自由奔跑”）;%设置导入HDL参数hdlset_param (“hdlcoder_led_blinking / led_counter / Blink_frequency”，．..“IOInterface”，'axi4'）;hdlset_param (“hdlcoder_led_blinking / led_counter / Blink_frequency”，．..“IOInterfaceMapping”，“x“100””）;hdlset_param (“hdlcoder_led_blinking / led_counter / Blink_frequency”，．..“IOInterfaceOptions”， {“RegisterInitialValue”, 5});%设置导入HDL参数hdlset_param (“hdlcoder_led_blinking / led_counter / Blink_direction”，．..“IOInterface”，'axi4'）;hdlset_param (“hdlcoder_led_blinking / led_counter / Blink_direction”，．..“IOInterfaceMapping”，“x“104””）;hdlset_param (“hdlcoder_led_blinking / led_counter Blink_direction,……“IOInterfaceOptions”， {“RegisterInitialValue”1});%设置Outport HDL参数hdlset_param (“hdlcoder_led_blinking / led_counter /领导”，“IOInterface”，'外部港口'）;%设置Outport HDL参数hdlset_param (“hdlcoder_led_blinking / led_counter / Read_back”，“IOInterface”，'axi4'）;hdlset_param (“hdlcoder_led_blinking / led_counter / Read_back”，．..“IOInterfaceMapping”，“x“108””）;hdlset_param (“hdlcoder_led_blinking / led_counter /读回,…“IOInterfaceOptions”， {“RegisterInitialValue”3});%%工作流配置设置使用默认设置构造工作流配置对象中国= hdlcoder。WorkflowConfig (“SynthesisTool”，“阿尔特拉第四的二世”，．..“TargetWorkflow”，'IP核心生成'）;%指定顶级项目目录中国。ProjectFolder =“hdl_prj”；%设置与合成工具版本相关的属性中国。所有owUnsupportedToolVersion = true;%设置要运行的工作流任务中国。RunTaskGenerateRTLCodeAndIPCore = true;中国。RunTaskCreateProject = true;中国。RunTaskGenerateSoftwareInterface = false;中国。RunTaskBuildFPGABitstream = true;中国。RunTaskProgramTargetDevice = false;％设置与生成RTL代码和IP核心任务相关的属性hwc.ipcorerepository =.'＇；中国。GenerateIPCoreReport = true;%设置“创建项目任务”相关的属性中国。目标= hdlcoder.Objective.AreaOptimized;％设置与生成软件界面模型任务相关的属性中国。操作系统='＇；中国。AddLinuxDeviceDriver = false;%设置Build FPGA Bitstream Task相关属性hwc.runexternalbuild = true;hwc.tclfileforsynthesisbuild = hdlcoder.buildoption.default;%验证工作流配置对象hWC.validate;%%运行工作流hdlcoder.runWorkflow (“hdlcoder_led_blinking / led_counter”、中国);

ip_core_gen_workflow_example.m

%--------------------------------------------------------------------------％HDL工作流脚本百分比在08/05/2018 18:14:14使用Matlab 9.5（R2018B Prereleaseasease）产生%该脚本使用以下参数值生成:% Filename: 'C:\Users\ggnanase\Desktop\R2018b\18b_models\ipcore_timing_failure\hdlworkflow_IO331.m'%覆盖:true%评论:正确% Headers: true% DUT: 'sfir_fixed/symmetric_fir'%需要查看修改后的工作流程，执行如下命令:％>> hwc.export（'dut'，'sfir_fixed / symmetric_fir'）;%--------------------------------------------------------------------------%%加载模型load_system (“sfir_fixed”）;%%将模型恢复为默认的HDL参数% hdlrestoreparams (' sfir_fixed / symmetric_fir ');%%模型HDL参数%%设置模型“sfir_fixed”HDL参数hdlset_param (“sfir_fixed”，“HDLSubsystem”，'sfir_fixed / symmetric_fir'）;hdlset_param (“sfir_fixed”，“SynthesisTool”，“Xilinx ISE”）;hdlset_param (“sfir_fixed”，“SynthesisToolChipFamily”，'spartan6'）;hdlset_param (“sfir_fixed”，“SynthesisToolDeviceName”，“xc6slx150”）;hdlset_param (“sfir_fixed”，“SynthesisToolPackageName”，'fgg676'）;hdlset_param (“sfir_fixed”，“SynthesisToolSpeedValue”，“3”）;hdlset_param (“sfir_fixed”，“TargetDirectory”，“hdl_prj \ hdlsrc”）;hdlset_param (“sfir_fixed”，“TargetFrequency”，75）;hdlset_param (“sfir_fixed”，“TargetPlatform”，“Speedgoat IO331”）;hdlset_param (“sfir_fixed”，“工作流程”，'金宝appSimulink实时FPGA I / O'）;%%工作流配置设置使用默认设置构造工作流配置对象中国= hdlcoder。WorkflowConfig (“SynthesisTool”，“Xilinx ISE”，“TargetWorkflow”，'金宝appSimulink实时FPGA I / O'）;%指定顶级项目目录中国。ProjectFolder =“hdl_prj”；中国。ReferenceDesignToolVersion ='＇；中国。IgnoreToolVersionMismatch = false;%设置与合成工具版本相关的属性中国。所有owUnsupportedToolVersion = true;%设置要运行的工作流任务中国。RunTaskGenerateRTLCode = true;中国。RunTaskCreateProject = true;中国。RunTaskPerformLogicSynthesis = true;中国。RunTaskPerformMapping = true;中国。RunTaskPerformPlaceAndRoute = true; hWC.RunTaskGenerateProgrammingFile = true; hWC.RunTaskGenerateSimulinkRealTimeInterface = true;设置与RunTaskCreateProject任务相关的属性中国。目标= hdlcoder.Objective.None;中国。AdditionalProjectCreationTclFiles ='＇；%设置与RunTaskPerformMapping任务相关的属性中国。SkipPreRouteTimingAnalysis = true;%设置与RunTaskPerformPlaceAndRoute任务相关的属性hwc.ignoreplaceandrouteErrors = false;%验证工作流配置对象hWC.validate;%%运行工作流hdlcoder.runWorkflow ('sfir_fixed / symmetric_fir'、中国);

slrt_workflow_example.m

%--------------------------------------------------------------------------％HDL工作流脚本%用MATLAB 9.5生成(R2018b预发布)在2018年8月05日18:14:33%该脚本使用以下参数值生成:％filename：'c：\ users \ ggnanase \ desktop \ r2018b \ 18b_models \ ipcore_timing_failure \ hdlworkflow_io333.m'%覆盖:true%评论:正确% Headers: true% DUT: 'sfir_fixed/symmetric_fir'%需要查看修改后的工作流程，执行如下命令:％>> hwc.export（'dut'，'sfir_fixed / symmetric_fir'）;%--------------------------------------------------------------------------%%加载模型load_system (“sfir_fixed”）;%%将模型恢复为默认的HDL参数% hdlrestoreparams (' sfir_fixed / symmetric_fir ');%%模型HDL参数%%设置模型“sfir_fixed”HDL参数hdlset_param (“sfir_fixed”，“HDLSubsystem”，'sfir_fixed / symmetric_fir'）;hdlset_param (“sfir_fixed”，“SynthesisTool”，“Xilinx Vivado”）;hdlset_param (“sfir_fixed”，“SynthesisToolChipFamily”，“Kintex7”）;hdlset_param (“sfir_fixed”，“SynthesisToolDeviceName”，“xc7k325t”）;hdlset_param (“sfir_fixed”，“SynthesisToolPackageName”，“ffg900”）;hdlset_param (“sfir_fixed”，“SynthesisToolSpeedValue”，' 2 '）;hdlset_param (“sfir_fixed”，“TargetDirectory”，“hdl_prj \ hdlsrc”）;hdlset_param (“sfir_fixed”，“TargetFrequency”, 100);hdlset_param (“sfir_fixed”，“TargetPlatform”，'speedgoat io333-325k'）;hdlset_param (“sfir_fixed”，“工作流程”，'金宝appSimulink实时FPGA I / O'）;%%工作流配置设置使用默认设置构造工作流配置对象中国= hdlcoder。WorkflowConfig (“SynthesisTool”，“Xilinx Vivado”，“TargetWorkflow”，'金宝appSimulink实时FPGA I / O'）;%指定顶级项目目录中国。ProjectFolder =“hdl_prj”；中国。ReferenceDesignToolVersion =“2017.4”；中国。IgnoreToolVersionMismatch = false;%设置与合成工具版本相关的属性中国。所有owUnsupportedToolVersion = true;%设置要运行的工作流任务中国。RunTaskGenerateRTLCodeAndIPCore = true;中国。RunTaskCreateProject = true;中国。RunTaskBuildFPGABitstream = true;中国。RunTaskGenerate金宝appSimulinkRealTimeInterface = true;%设置与runtaskgeneratertlcodeanddipcore任务相关的属性hwc.ipcorerepository =.'＇；中国。GenerateIPCoreReport = true;中国。GenerateIPCoreTestbench = false;中国。CustomIPTopHDLFile ='＇；中国。AXI4RegisterReadback = false;中国。IPDataCaptureBufferSize ='128'；设置与RunTaskCreateProject任务相关的属性中国。目标= hdlcoder.Objective.None;中国。AdditionalProjectCreationTclFiles ='＇；中国。EnableIPCaching = true;%设置与RunTaskBuildFPGABitstream任务相关的属性hwc.runexternalbuild = false;hwc.tclfileforsynthesisbuild = hdlcoder.buildoption.default;HWC.CustombuildTclfile ='＇；中国。ReportTimingFailure = hdlcoder.ReportTiming.Error;%验证工作流配置对象hWC.validate;%%运行工作流hdlcoder.runWorkflow ('sfir_fixed / symmetric_fir'、中国);

slrt_workflow_example.m