Generate Target-Independent HDL Code with Native Floating-Point

HDL Coder™ native floating-point technology can generate target-independent HDL code from your floating-point design. You can synthesize your floating-point design on any generic FPGA or ASIC. Floating-point designs have better precision, higher dynamic range, and a shorter development cycle than fixed-point designs. If your design has complex math and trigonometric operations, use native floating-point technology.

HowHDL CoderGenerates Target-Independent HDL Code

This figure shows how HDL Coder generates code with the native floating-point technology.

TheUnpackandPackblocks convert the floating-point types to the sign, exponent, and mantissa. In the figure,S,E, andMrepresent the sign, exponent, and mantissa respectively. This interpretation is based on the IEEE-754 standard of floating-point arithmetic.

TheFloating-Point Algorithm Implementationblock performs computations on theS,E, andM. With this conversion, the generated HDL code is target-independent. You can deploy the design on any generic FPGA or an ASIC.

Enable Native Floating Point and Generate Code

You can generate code in the Configuration Parameters dialog box or at the command line.

To specify the native floating-point settings and generate HDL code in the Configuration Parameters dialog box:

In theAppstab, selectHDL Coder. TheHDL Codetab appears.
ClickSettings. In theHDL Code Generation>Floating Pointpane, forLibrary, selectNative Floating Point.
Specify theLatency Strategyto map your design to maximum or minimum latency or no latency.
If you have denormal numbers in your design, select处理Denormals. Denormal numbers are numbers that have an exponent field equal to zero and a nonzero mantissa field. See处理Denormals.
If your design has multipliers, to specify how you want HDL Coder to implement the multiplication operation, use theMantissa Multiplier Strategy. SeeMantissa Multiplier Strategy.
To share floating-point resources, on theHDL Code Generation>Optimizations>Resource Sharingtab, make sure that you selectFloating-point IPs. The number of blocks that get shared depends on theSharingFactorthat you specify for the subsystem.
ClickApply. In theHDL Codetab, clickGenerate HDL Code.

To generate HDL code at the command line, use thehdlcoder.createFloatingPointTargetConfigfunction. You can use this function to create anhdlcoder.FloatingPointTargetConfigobject for the native floating-point library.

nfpconfig = hdlcoder.createFloatingPointTargetConfig('NATIVEFLOATINGPOINT'); hdlset_param('sfir_single','FloatingPointTargetConfiguration', nfpconfig);

Optionally, you can specify the latency strategy and whether you want HDL Coder to handle denormal numbers in your design:

nfpconfig.LibrarySettings.HandleDenormals ='on'; nfpconfig.LibrarySettings.LatencyStrategy ='MAX';

To learn how you can verify the generated code, seeVerify the Generated Code from Native Floating-Point.

View Code Generation Report

To view the code generation reports of floating-point library mapping, before you begin code generation, enable generation of the Resource Utilization Report and Optimization Report. To enable the reports, on theHDL Codetab, clickSettings>Report Optionsin the Configuration Parameters dialog box, on theHDL Code Generationpane, enable生成资源利用率报告andGenerate optimization report. For more information, seeCreate and Use Code Generation Reports.

To see the list of native floating-point operators that HDL Coder supports and the floating-point operators to which your Simulink^®blocks mapped to, in the Code Generation Report, selectNative Floating-Point Resource Report.

A detailed report shows the various resources that the floating-point blocks use on the target device that you specify. HDL code generation from a native floating point design uses dynamic shift operations for aligning mantissa based on exponent values. Because these dynamic shifters are resource-expensive in the model, they are reported separately from static shift operators. For more information on dynamic and static shifters, seeTiming and Area Report.

To see the native floating-point settings that you applied to the model and whether HDL Coder successfully generated HDL code, in the Code Generation Report, selectTarget Code Generation.

Analyze Results

Floating point operators have a latency. If your Simulink model does not have delays, when you generate HDL code, the code generator figures out the operator latency and delay balances parallel paths. Consider this Simulink model that has twosingleinputs and gives asingleoutput.

TheMATLAB Functionblock in the Simulink model contains this code.

functiony = fcn(u, w)%#codegeny1 = (u+w) * 20; y2 = w^16; y3 = (u-w) / 10; y = y1 + y2 - y3;

When you generate HDL code, the code generator maps the blocks in your Simulink model to synthesizable native floating-point operators. To see how the code generator implemented the floating-point operations, open the generated model. The blocksNFP math,NFP Sqrt, andNFP trig对应的浮点implementation of theReciprocal Sqrt,Reciprocal,sin, andcosblocks respectively in your original model.

Every floating-point operator has a latency. The code generator inserted an additional matching delay because the latency of theReciprocal Sqrtis30and latency ofReciprocalis31. The operator latency is equal to theDelay lengthof theDelayblock inside thatNFPblock. For example, if you double-click theNFP sqrtblock, you can get the latency by looking at theDelay lengthof theDelayblock. SeeLatency Values of Floating-Point Operators.

When you useMATLAB Functionblocks with floating-point data types, HDL Coder uses theMATLAB Datapatharchitecture. This architecture treats theMATLAB Functionblock like a regularSubsystemblock. When you generate code, the code generator maps the basic operations such as addition and multiplication to the corresponding native floating-point operators. Open theMATLAB Functionsubsystem to see how the code generator implemented theMATLAB Functionblock.